Latest List of VLSI Projects for Electronics Engineering Students

VLSI – Very Large Scale integration technology involves designing integrated circuits (ICs) by combining thousands of transistors logically into a single chip by different logic circuits. These ICs eventually reduce the occupied circuit space when compared to the circuits with conventional ICs. Computational power and space utilizations are the main challenges of the VLSI design.

Implementing VLSI projects opens up a challenging and bright career for students as well as researchers. Some of the new trending areas of VLSI are Field Programmable Gate Array applications (FPGA), ASIC designs and SOCs. A list of some of the VLSI projects is given below for those students who are earnestly seeking projects in this field.

1. FPGA-Based Fault Emulation of Synchronous Sequential Circuits
2. Pragmatic Integration of SRAM Row Cache in Heterogeneous 3-D DRAM Architecture Using TSV
3. Built-in Self-Test Technique for Diagnosis of Delay Faults in Cluster-Based Field Programmable Gate Arrays
4. ASIC Design of Complex Multiplier
5. A Low Cost VLSI Implementation for Efficient Removal of Impulse Noise
6. FPGA Based Space Vector PWM Control IC For Three Phase Induction Motor Drive
7. VLSI Implementation of Auto Correlator and CORDIC Algorithm for OFDM Based WLAN
8. Automatic Road Extraction Using High Resolution Satellite Images
9. VHDL Design for Image Segmentation Using Gabor Filter for Disease Detection
10. A Low Complexity Turbo Decoder Architecture for Energy Efficient Wireless Sensor Networks
11. Improvement of The Orthogonal Code Convolution Capabilities Using FPGA Implementation
12. Design and Implementation of Floating Point ALU
13. CORDIC Design for Fixed Angle of Rotation
14. Product Reed-Solomon Codes for Implementing NAND Flash Controller on FPGA Chip
15. Statistical SRAM Read Access Yield Improvement Using Negative Capacitance Circuits
16. Power Management of MIMO Network Interfaces on Mobile Systems
17. Design of Data Encryption Standard for Data Encryption
18. Low Power and Area Efficient Carry Select Adder
19. Synthesis and Implementation of UART Using VHDL Codes
20. Improved Architectures for a Fused Floating-Point Add-Subtract Unit
21. An FPGA Based 1-Bit All Digital Transmitter Employing Delta-Sigma Modulation with RF Output for SDR
22. Optimizing Chain Search Usage in The BCH Decoder for High Error Rate Transmission
23. Digital Design of DS-CDMA Transmitter Using Verilog HDL and FPGA
24. Design and Implementation of Efficient Systolic Array Architecture
25. A VLSI-Based Robot Dynamics Learning Algorithm
26. A Versatile Multimedia Functional Unit Design Using the Spurious Power Suppression Technique
27. Design of Bus Bridge between AHB and OCP
28. Behavioral Synthesis of Asynchronous Circuits
29. Speed Optimization of a FPGA Based Modified Viterbi Decoder
30. Implementation of I2C Interface
31. A High-Speed/Low-Power Multiplier Using an Advanced Spurious Power Suppression Technique
32. Clamping Virtual Supply Voltage of Power Gated Circuits for Active Leakage Reduction and Gate Oxide Reliability
33. FPGA Based Power Efficient Channelizer for Software Defined Radio
34. VLSI Architecture and FPGA Prototyping of a Digital Camera for Image Security and Authentication
35. Operation Improvement of Indoor Robot
36. Design and Implementation of an ON-Chip Permutation Network for Multiprocessor System On-Chip
37. A Symbol-Rate Timing Synchronization Method for Low Power Wireless OFDM Systems
38. DMA Controller (Direct Memory Access ) Using VHDL/VLSI
39. Reconfigurable FFT Using CORDIC Based Architecture for MIMI-OFDM Receivers
40. Spurious Power Suppression Technique for Multimedia/DSP Applications
41. Efficiency of BCH Codes in Digital Image Watermarking
42. Dual Data Rate SD RAM Controller
43. Implementing Gabor Filter for Fingerprint Recognition Using Verilog HDL
44. Design of a Practical Nanometer Scale Redundant via Aware Standard Cell Library for Improved Redundant via 1 Insertion Rate
45. A Lossless Data Compression and Decompression Algorithm and Its Hardware Architecture
46. A Framework for Correction of Multi-Bit Soft Errors
47. Viterbi-Based Efficient Test Data Compression
48. Implementation of FFT/IFFT Blocks for OFDM
49. Wavelet Based Image Compression by VLSI Progressive Coding
50. VLSI Implementation of Fully Pipelined Multiplier Less 2d DCT/IDCT Architecture for Jpeg

After spending your valuable time while going through this list, we believe that you have got a fairly good idea of selecting the project topic of your choice from the VLSI projects’ list, and hope that you have enough confidence to take up any topic from the list. For further details and help about these projects you can write to us in the comments section given below.

source: https://www.elprocus.com/ieee-based-list-of-best-vlsi-projects-for-engineering-students-in-2014/

Get to Market Faster with Modular Circuit Design

by Craig Armenti, Zuken USA, Inc.

The concept of designing, validating and then reusing functional blocks in integrated circuits (ICs) has been entrenched in the electronics industry for decades.  Software development has a similar model utilizing libraries of common function calls or objects.  However, the concept of reusing printed circuit board (PCB) modules is much less common. Reusing PCB modules for common or commodity functions offers considerable advantages, for example avoiding potential signal integrity or thermal problems, by utilizing circuit data whose performance has been proven in previous generations of products. The key to successful modular circuit design is a data management system that can store and control access to modular reusable blocks, manage information that is critical to design reuse, such as the layer structure of a routed block, and interface easily with the circuit design software. The end result is a reduction in time during schematic capture and PCB design, along with fewer design errors, making it possible to bring quality products to market faster. 

Circuit design challenges

The volume and frequency of new product introductions require new design methodologies.  Reuse is becoming a competitive requirement. The size and complexity of today’s electronics products makes it impossible to generate a new design from scratch each time. Instead designs are largely, created by selecting and combining existing blocks of circuitry. The availability, variety and quality of these reuse blocks depends on the company.  Some have embraced this new methodology and others have not.

This topic is getting more attention because much of the electronic content in a wide range of electronics products has been commoditized with the consolidation of increasing amounts of functionality in application processors or system-on-chips (SoCs) and their associated reference designs.  Along with this consolidation is the standardization of busses and protocols allowing for even more reuse.

Today, circuit designers face challenges such as the increasing density of nets, the proliferation of electrical constraints along with reductions in PCB size – not to mention stricter-than-ever requirements to maintain reliability, electrical response, manufacturability and compliance. IC and field-programmable gate array (FPGA) vendors are implementing serial asynchronous architectures operating at higher speeds than ever, creating new challenges in meeting jitter and bit error rate specifications. The increase in data rates, faster component edge rates and major changes in I/O architecture put additional pressures on circuit designers. An increasing proportion of today’s electronic products require high-speed design techniques to ensure that PCB guidelines and high-speed requirements are met, however, they still need to be produced quickly and inexpensively.

The amount of time and effort required to overcome these challenges is significant. Experienced engineers in circuit design put in time upfront, and then additional effort is spent in simulating circuit performance from a signal integrity, power integrity and thermal standpoint. Often many iterations are required in order to find a design that successfully passes the simulation requirements. The next step is building a prototype of the PCB and performing an exhaustive series of tests to validate its performance. Often additional changes are required during the prototyping phase. Of course, the greatest test of all comes when the product is delivered to the customer and achieves success in the marketplace.

Current circuit reuse methods

When the time comes to produce a related product, such as a next generation replacement or a variant targeted at a niche market, it is common practice to reuse the circuitry in the original design. This is usually accomplished by copying and modifying the original design, or by utilizing predefined modules from the original design. For example, a new cell phone variant might utilize the same baseband, Bluetooth and Wi-Fi modules as the previous design, combined with a new RF section. This is because creating a related product from scratch would take a considerable amount of time and potentially introduce design errors. 

Another approach circuit engineers may use is to copy and paste from previous related designs; however this approach has several drawbacks. In larger companies, it can often be difficult to find a related design that fits the specific requirements of the current project. There’s always the potential for the designer to inadvertently reuse a version of a related design that does not include the latest changes and thereby replicate problems resolved in the latest version of the earlier design. Another problem with the copy and paste method is that the knowledge developed in creating the original design is typically lost. The copied blocks lack intelligence such as the underlying design methodology and best practices. The copy and paste approach also lacks traceability. It’s typically necessary to rely on the engineer who created the original design to determine the source of individual modules. If a problem is discovered with the source module at a later date, there’s a good chance that the designers of the new module will not even be aware of the change. In that case, the error that stimulated the original change will crop again and have to be resolved in the copy, hopefully before the product is released to customers.

Managing modular circuit blocks

Fig. 1 Reusable modular schematic and PCB blocks

These problems are being addressed by data management software that stores reusable circuitry in the form of modular blocks, greatly simplifying the process of reusing existing PCB schematics, parts lists and layouts. The new generation of data management software controls access to circuit blocks by providing information only to authorized users and ensuring that only users who are authorized editors are allowed to make changes. To perform changes, a modular block must be checked out. While a block is checked out, other users are prevented from making changes to it in order to ensure the integrity of the block. Furthermore, the data management software can be configured to require either one or a series of approvals when a change is made to a modular block. The modified block is then automatically routed to the designated approvers. 

Reusable modular blocks can be created in two different ways – either the top-down or bottom-up approach. The top-down approach involves partitioning the design in the early stages of the design process, creating the block diagram, then adding the appropriate circuitry to each block. When the blocks are validated and the design is completed, the parts list, schematic, and layout of each block is then registered in the data management system along with its metadata. Metadata allows the block to be found easily and contains detail such as which products the block is used in, the engineers involved in its design and the approval chain. Conversely, the bottom-up approach starts with creating and validating the circuitry. After the circuit validation is completed it is then partitioned into blocks.

Overall the top-down approach is usually the most effective, but it does require more time for planning. The payoff is that the blocks produced by this method are typically more suitable for reuse, so considerable time is saved in the design of variants that utilize these blocks.

Streamlining the design process

Figure 2 Partitioned designs facilitate circuit reuse

The modular design approach is not a panacea, but it can substantially streamline the design process. Let’s look at how it could be used in circuit design for the cell phone example mentioned earlier. In this case, let’s assume that the predecessor design has been partitioned into blocks representing the RF, baseband, Wi-Fi, Bluetooth and other sections. The engineer working on the new variant can easily call up these modules by searching the data management system on the product name. The engineer can then check the documentation stored in the data management system for each module they plan to use to ensure it is a fit for the new design. Then the engineer can drop the modular blocks that will be used without modification into the new design. The parts list, schematic and layout of each modular block will all be incorporated into the new design.

The engineer can then design the new RF block and any other new blocks needed, either from scratch or by modifying existing blocks. They can then connect the sections together and route the new areas of the design. Next come checks on issues such as signal integrity and thermal management, while focusing on the newly routed areas. Of course it is still necessary to do basic simulation of the complete design because even though we know that each individual block works fine, there’s the small possibility that combining them might cause a problem.

In conclusion, modular circuit design offers a number of compelling advantages that are leading to its rapidly increasing adoption. The ability to share circuit modules across many products and projects can reduce the manpower required for future projects, thus reducing development costs and improving productivity. Test and regulatory compliance time is also reduced through the use of proven design blocks. The reduction in design time makes it possible to bring products to market faster which helps increase revenues and enables new products to gain market share before they face serious competition. Modular circuit reuse also reduces errors by allowing designers to utilize proven designs wherever possible. Now is the time to begin utilizing modular design to enable your teams to increase the speed of developing and releasing boards.

Source: http://www.techfocusmedia.net/archives/articles/20150122-zuken

New Circuit Design Promises Cheaper Computer Chips

Scientists of the Massachusetts Institute of Technology (MIT) have created a new circuit design that can greatly reduce the manufacturing costs of computer chips.

The researchers presented their findings in the journal Nano Letters.

Computer chips with superconducting circuits, or circuits with zero electrical resistance, are estimated to be 50 to 100 times as energy-efficient as today’s computer chips. Superconducting chips also promise greater processing power, with superconducting circuits that use so-called Josephson junctions already having been clocked at 770 gigahertz, or 500 times the speed of the chip that can be found in Apple’s iPhone 6.

Josephson-junction chips are however large and hard to make. Most problematic of all is that the minute electrical currents that Josephson-junction chips generate after computations are very hard to detect.

The new circuit design for computer chips created by the researchers at MIT probably won’t top the speeds of today’s computer chips just yet, but it could solve the problem of reading out the results of calculations performed with so called Josephson junctions.

MIT researchers Adam McCaughan, a graduate student in electrical engineering, and his advisor, professor of electrical engineering and computer science Karl Berggren call their newly designed device the nanocryotron, named after the cryotron, an experimental computing circuit developed in the 1950s by MIT professor Dudley Buck.

“The superconducting-electronics community has seen a lot of new devices come and go, without any development beyond basic characterization,” McCaughan says. “But in our paper, we have already applied our device to applications that will be highly relevant to future work in superconducting computing and quantum communications.”

The most promising application of the nanocryotron, or nTron, could be making calculations performed by Josephson junctions accessible to the outside world. In experiments, McCaughan demonstrated that currents even smaller than those that are generated by Josephson-junction devices were adequate to switch the nTron from a conductive to a nonconductive state, big enough to carry information to other devices on a computer motherboard.

“I think this is a great device,” says Oleg Mukhanov, chief technology officer of Hypres, a superconducting-electronics company whose products rely on Josephson junctions. “We are currently looking very seriously at the nTron for use in memory.”
“There are several attractions of this device,” Mukhanov says. “First, it’s very compact, because after all, it’s a nanowire. One of the problems with Josephson junctions is that they are big. If you compare them with CMOS transistors, they’re just physically bigger. The second is that Josephson junctions are two-terminal devices. Semiconductor transistors are three-terminal, and that’s a big advantage. Similarly, nTrons are three-terminal devices.”

Source: http://computerstories.net/new-circuit-design-promises-cheaper-computer-chips/

ACCESSIBLE CIRCUIT DESIGN BRINGS ENDLESS POSSIBILITIES

Inside every iPhone, behind every piece of computer equipment and at the heart of everything in electrical and computer engineering, there's a circuit to carry electric current. From the simple to the complex, circuits are everywhere—and startup company AgIC is making it easier than ever to work with them.

Using silver nano-particle ink, AgIC produces felt-tip pens and cartridges for home inkjet printers to make circuit design and testing simple for engineering experts, as well as novices. CMU alumnus Yuki Nishida, a 2014 graduate of the Information Networking Institute's Master of Science in Information Technology (MSIT) program, is one of the founders and currently head of the company's American office.

The pen can make live circuits on coated photo paper, and the printer works with coated photo paper or acetate. You can trace a simple line to conduct power from a source, such as a battery, to activate a small element like an LED when the circuit is completed. But when the path isn't drawn correctly, nothing works, and you have to completely start over, which makes the cost of failure pretty high.

That's where the eraser pen, and a now completed Kickstarter campaign, come in. "What we hope to do is make people feel like making circuits is easy," Nishida says. Mistakes are very easy to make, especially when you're learning, he says, but an eraser that can remove small errors in circuits—hand-drawn or printed—makes it possible to edit circuits as you go.

AgIC's first Kickstarter in early 2014 was a success, and the recent eraser campaign ran through January 13. In mid-December, it was more than two-thirds of the way to completing the $10,000 goal and had been chosen as a staff pick on the popular crowdfunding site.

Through Nishida's connections with CMU-SV, the project has received lots of support and exposure on campus. Faculty member Stuart Evans of the Integrated Innovation Institute, an expert on startup strategies and high-tech entrepreneurship, has offered his guidance.Electrical and Computer Engineering Ph.D. student Irina Brinster has given her input on using AgIC for antenna designs, taking advantage of the pen's ability to change signals by adding to the lines.

Information Networking Institute MSIT students Yun Cao and Tomokazu Yoshida worked with AgIC on an independent study project in Fall 2014, supporting the company's education and outreach programs and helping make new designs.

In the past year, AgIC has been offering demos and participating in events throughout the Bay Area to find new users and future engineers. Education is a big potential market, considering national initiatives to improve STEM education and computer programming opportunities for students. A simple, interactive tool like the AgIC pen is a great gateway project for engineering, as Cao and Yoshida saw at outreach events. "You definitely see it triggers interest in the kids," Cao says.

CMU-SV's Circuit Runner team used an AgIC pen and LED as part of their hackathon-winning educational project in October. The students and volunteers have also run demos at San Jose's Tech Museum and at local exhibitions like the Maker Faire.

Adoption in the maker culture is another big market, also in line with growing national exposure and reflected in Carnegie Mellon's efforts to encourage makers. Used with a small controller like an Arduino, an AgIC drawing can connect with more complex components and devices—like as a touch sensor interface, as shown on a video on AgIC's site, or to power a speaker.

Nishida sees a lot of potential in AgIC's future. He says they'd love to talk with the agencies planning ventures to Mars, since some of the major limitations on long-range space missions will be equipment and space. Like 3-D printers, this small, multitasking technology could take the place of larger, dedicated machinery.  

But they're also happy to see more people here on Earth getting interested first. "We want more people to start making and try different things," Nishida says.

Collaboration Note: AgIc is the result of collaboration between faculty and students from Carnegie Mellon University in Silicon Valley, the Integrated Innovation Institute, the Department of Electrical and Computer Engineering, and the Information Networking Institute.

Story originally published at: www.cmu.edu/silicon-valley

Circuit gates pulse train without truncating

Source: http://www.edn.com/design/systems-design/4438302/Circuit-gates-pulse-train-without-truncating

To gate an integral clock pulse sequence from a continuous source without distorting pulse duration and number is not a trivial task. In most cases, a simple AND gate will cause problems, see Figure 1.

Clock pulses pass through the AND gate as long as the asynchronous strobe E is high. If loss or distortion of even one pulse is critical, then the simple AND gate is unsuitable, as the first and the last pulse in the burst will often be distorted (shorter than usual pulse) due to the lack of synchronization between clock andE.

This Design Idea demonstrates a mathematical approach to synthesize an asynchronous gated circuit able to gate an accurate pulse train from a clock signal without distorting pulse duration. Such circuits are called quantizers.

Figure 1  Two ways of gating pulse train, using gate signal E and an AND gate (Y output), or a quantizer (blue)

Let’s make a state transition table based on the operational principle of a quantizer:

Figure 2  Asynchronous finite-state machine (FSM) transition primary table, where 1,2,3,4,5,6,7, the numbers of stable FSM states, are circled (G is the clock input)

Using Figure 2, let’s make final pairs tables according to Mealy and Moore: 

Figure 3  Final pairs tables by Mealy (left) and Moore (right), where:

• MC1: 2-5-6-7 and MC2: 1-3-4 are maximum compatible sets (by Mealy)
• MC1: 5-7, MC2: 1-2-6 and MC3: 1-3-4 are maximum compatible sets (by Moore)

As we can see from Figure 3, total coverage by Moore requires a greater number of maximum compliant subsets, i.e., it’s worse. On the other hand, the first state is alternatively a part of sets MC2 and MC3, which presents opportunities for extra circuit optimization. However, we shall not consider this further.

Now, it’s easy to draw a compressed state transition table and Karnaugh-Veitch maps for the Z-coding memory element and output gated signal Y:

 

Figure 4  Map of Z-coding (by Mealy), compressed state transition table, and Z-Y Karnaugh-Veitch maps

Bearing in mind the Karnaugh-Veitch maps, let’s write down logic equations for the synthesized circuit:

The minterm [/E · z] for z⁺ in this formula is not redundant as it may seem. It plays the important role of a counter-race bridge between minterms [/G · /E] and [G · z], eliminating their consecutive races at all edges of G.

Figure 5  Example implementation of the quantizer, where:

• /E = inverted input of the asynchronous strobe signal
• G = clock
• Y = quantizer output

It is possible to add some extra features – for example, FLAG. When FLAG is low, the first pulsein the burst is not cut, but incorporated in the burst without affecting its duration. When FLAG is high, the first pulse is cut and excluded from the burst. State of the FLAG should be kept unchanged till the next strobe pulse, so your equipment has enough time to read it and use for further processing.

This type of quantizer may be useful in designs sensitive not only to the number of pulses in the burst, but to the pulse phase; for example, in radar equipment.

The Future of Very Large-Scale Integration (VLSI) Technology

The historical growth of IC computing power has profoundly changed the way we create, process, communicate, and store information. The engine of this phenomenal growth is the ability to shrink transistor dimensions every few years. This trend, known as Moore’s law, has continued for the past 50 years. The predicted demise of Moore’s law has been repeatedly proven wrong thanks to technological breakthroughs (e.g., optical resolution enhancement techniques, high-k metal gates, multi-gate transistors, fully depleted ultra-thin body technology, and 3-D wafer stacking). However, it is projected that in one or two decades, transistor dimensions will reach a point where it will become uneconomical to shrink them any further, which will eventually result in the end of the CMOS scaling roadmap. This essay discusses the potential and limitations of several post-CMOS candidates currently being pursued by the device community.

Steep transistors: The ability to scale a transistor’s supply voltage is determined by the minimum voltage required to switch the device between an on- and an off-state. The sub-threshold slope (SS) is the measure used to indicate this property. For instance, a smaller SS means the transistor can be turned on using a smaller supply voltage while meeting the same off current. For MOSFETs, the SS has to be greater than ln(10) × kT/q where k is the Boltzmann constant, T is the absolute temperature, and q is the electron charge. This fundamental constraint arises from the thermionic nature of the MOSFET conduction mechanism and leads to a fundamental power/performance tradeoff, which could be overcome if SS values significantly lower than the theoretical 60-mV/decade limit could be achieved. Many device types have been proposed that could produce steep SS values, including tunneling field-effect transistors (TFETs), nanoelectromechanical system (NEMS) devices, ferroelectric-gate FETs, and impact ionization MOSFETs. Several recent papers have reported experimental observation of SS values in TFETs as low as 40 mV/decade at room temperature. These so-called “steep” devices’ main limitations are their low mobility, asymmetric drive current, bias dependent SS, and larger statistical variations in comparison to traditional MOSFETs.

Spin devices: Spintronics is a technology that utilizes nano magnets’ spin direction as the state variable. Spintronics has unique properties over CMOS, including nonvolatility, lower device count, and the potential for non-Boolean computing architectures. Spintronics devices’ nonvolatility enables instant processor wake-up and power-down that could dramatically reduce the static power consumption. Furthermore, it can enable novel processor-in-memory or logic-in-memory architectures that are not possible with silicon technology. Although in its infancy, research in spintronics has been gaining momentum over the past decade, as these devices could potentially overcome the power bottleneck of CMOS scaling by offering a completely new computing paradigm. In recent years, progress has been made toward demonstration of various post-CMOS spintronic devices including all-spin logic, spin wave devices, domain wall magnets for logic applications, and spin transfer torque magnetoresistive RAM (STT-MRAM) and spin-Hall torque (SHT) MRAM for memory applications. However, for spintronics technology to become a viable post-CMOS device platform, researchers must find ways to eliminate the transistors required to drive the clock and power supply signals. Otherwise, the performance will always be limited by CMOS technology. Other remaining challenges for spintronics devices include their relatively high active power, short interconnect distance, and complex fabrication process.

Flexible electronics: Distributed large area (cm2-to-m2) electronic systems based on flexible thin-film-transistor (TFT) technology are drawing much attention due to unique properties such as mechanical conformability, low temperature processability, large area coverage, and low fabrication costs. Various forms of flexible TFTs can either enable applications that were not achievable using traditional silicon based technology, or surpass them in terms of cost per area. Flexible electronics cannot match the performance of silicon-based ICs due to the low carrier mobility. Instead, this technology is meant to complement them by enabling distributed sensor systems over a large area with moderate performance (less than 1 MHz). Development of inkjet or roll-to-roll printing techniques for flexible TFTs is underway for low-cost manufacturing, making product-level implementations feasible. Despite these encouraging new developments, the low mobility and high sensitivity to processing parameters present major fabrication challenges for realizing flexible electronic systems.

CMOS scaling is coming to an end, but no single technology has emerged as a clear successor to silicon. The urgent need for post-CMOS alternatives will continue to drive high-risk, high-payoff research on novel device technologies. Replicating silicon’s success might sound like a pipe dream. But with the world’s best and brightest minds at work, we have reasons to be optimistic.

Author’s Note: I’d like to acknowledge the work of PhD students Ayan Paul and Jongyeon Kim.

Programme to train engineers for the VLSI segment to be launched V. SRIDHAR

The burgeoning bill for electronics imports and the government’s recent efforts to establish indigenous capacities for semiconductor manufacturing may be a step in the right direction, but the industry complains that the shortage of skilled manpower is still a major worry.

In an effort to bridge the gap, the Institute of Electrical and Electronics Engineers (IEEE) will start a unique course for engineers trying to enter the Very-Large-Scale Integration (VLSI) segment of the industry, the basic element in electronics.

VLSI is the process of manufacturing integrated circuits by combining thousands of transistors in a single chip. VLSI came into being in the 1970s when complex semiconductor and communication technologies were being developed. The microprocessor is an example of a VLSI device.

Collaborative effort

The Indian arm of the IEEE, a not-for-profit organisation based in New York, has entered into a collaboration with the R.V.-VLSI Design Centre, a unit of the Rashtreeya Shiksana Samiti Trust, which manages 28 educational institutions.

David Goldstein, director, New Product Development, IEEE, said the “blended learning” programme was designed by the R.V. College of Engineering, but the course content was “designed and validated by educational and industry experts from all over the world”. The IEEE had reviewed the programme, which included an online learning component and work in the laboratory.

Mr. Goldstein said the choice of location was critically dependent on not only the availability of lab facilities but also the availability of Electronic Design Automation tools, a category of software tools used for designing electronic systems such as printed circuit boards and integrated circuits. The tools would also be “vendor-neutral”, he said.

The existing cluster of VLSI designing companies in Bangalore was the reason Bangalore had been chosen as the launch pad for the initiative, Mr. Goldstein said.

“We are seeding this in Bangalore because we were satisfied by the quality of the laboratory facilities that were available at R.V. College, he said. The course is likely to be launched between April and June.

Mr. Goldstein said the programme targeted three sets of students: undergraduates, postgraduates and industry professionals. He said the professionals would go through “advanced domain modules, which is more appropriate to the skills that they already have”. In the first year, the programme would not offer certification. “Certification will happen in due course, but for now, we only plan to validate the programme so that there is acceptance in the industry,” he explained.

Increasing demand

At present, there were around 35,000 VLSI engineers in India, and the demand was increasing at an annual rate of about 10 per cent, Mr. Goldtsein said. The IEEE, he said, had plans to not only extend the programme to Mumbai, Hyderabad, Chennai and the National Capital Region, but to use India as a launch pad to expand overseas to Sri Lanka, Vietnam and other countries in South-east Asia.

“But we are now moving in a calibrated manner because we have to ensure that the facilities are available before we launch in other locations,” he said. Although he did not reveal the cost of the course, he said they would be “cost effective” and follow what the IEEE called the “emerging markets pricing schedule”.

Sponsorship by companies had the potential to reduce costs further, he said.

Intake

The intake was likely to be limited to 500 students, said Venkatesh Prasad, CEO of the design centre, even though this could be extended to 1,000 students soon. He said the constraint on intake was set by the availability of the “sophisticated tools” that were necessary for such a programme, the access to nanotech fabrication units, and access to people from the industry.

The campus was being established at Jayanagar because it was close to the electronics cluster in Electronics City, he said.

Keywords: IEEE, VLSI

Source: http://www.thehindu.com/sci-tech/technology/programme-to-train-engineers-for-the-vlsi-segment-to-be-launched/article5546069.ece