Circuit gates pulse train without truncating

Source: http://www.edn.com/design/systems-design/4438302/Circuit-gates-pulse-train-without-truncating

To gate an integral clock pulse sequence from a continuous source without distorting pulse duration and number is not a trivial task. In most cases, a simple AND gate will cause problems, see Figure 1.

Clock pulses pass through the AND gate as long as the asynchronous strobe E is high. If loss or distortion of even one pulse is critical, then the simple AND gate is unsuitable, as the first and the last pulse in the burst will often be distorted (shorter than usual pulse) due to the lack of synchronization between clock andE.

This Design Idea demonstrates a mathematical approach to synthesize an asynchronous gated circuit able to gate an accurate pulse train from a clock signal without distorting pulse duration. Such circuits are called quantizers.

Figure 1  Two ways of gating pulse train, using gate signal E and an AND gate (Y output), or a quantizer (blue)

Let’s make a state transition table based on the operational principle of a quantizer:

Figure 2  Asynchronous finite-state machine (FSM) transition primary table, where 1,2,3,4,5,6,7, the numbers of stable FSM states, are circled (G is the clock input)

Using Figure 2, let’s make final pairs tables according to Mealy and Moore: 

Figure 3  Final pairs tables by Mealy (left) and Moore (right), where:

• MC1: 2-5-6-7 and MC2: 1-3-4 are maximum compatible sets (by Mealy)
• MC1: 5-7, MC2: 1-2-6 and MC3: 1-3-4 are maximum compatible sets (by Moore)

As we can see from Figure 3, total coverage by Moore requires a greater number of maximum compliant subsets, i.e., it’s worse. On the other hand, the first state is alternatively a part of sets MC2 and MC3, which presents opportunities for extra circuit optimization. However, we shall not consider this further.

Now, it’s easy to draw a compressed state transition table and Karnaugh-Veitch maps for the Z-coding memory element and output gated signal Y:

 

Figure 4  Map of Z-coding (by Mealy), compressed state transition table, and Z-Y Karnaugh-Veitch maps

Bearing in mind the Karnaugh-Veitch maps, let’s write down logic equations for the synthesized circuit:

The minterm [/E · z] for z⁺ in this formula is not redundant as it may seem. It plays the important role of a counter-race bridge between minterms [/G · /E] and [G · z], eliminating their consecutive races at all edges of G.

Figure 5  Example implementation of the quantizer, where:

• /E = inverted input of the asynchronous strobe signal
• G = clock
• Y = quantizer output

It is possible to add some extra features – for example, FLAG. When FLAG is low, the first pulsein the burst is not cut, but incorporated in the burst without affecting its duration. When FLAG is high, the first pulse is cut and excluded from the burst. State of the FLAG should be kept unchanged till the next strobe pulse, so your equipment has enough time to read it and use for further processing.

This type of quantizer may be useful in designs sensitive not only to the number of pulses in the burst, but to the pulse phase; for example, in radar equipment.

The Future of Very Large-Scale Integration (VLSI) Technology

The historical growth of IC computing power has profoundly changed the way we create, process, communicate, and store information. The engine of this phenomenal growth is the ability to shrink transistor dimensions every few years. This trend, known as Moore’s law, has continued for the past 50 years. The predicted demise of Moore’s law has been repeatedly proven wrong thanks to technological breakthroughs (e.g., optical resolution enhancement techniques, high-k metal gates, multi-gate transistors, fully depleted ultra-thin body technology, and 3-D wafer stacking). However, it is projected that in one or two decades, transistor dimensions will reach a point where it will become uneconomical to shrink them any further, which will eventually result in the end of the CMOS scaling roadmap. This essay discusses the potential and limitations of several post-CMOS candidates currently being pursued by the device community.

Steep transistors: The ability to scale a transistor’s supply voltage is determined by the minimum voltage required to switch the device between an on- and an off-state. The sub-threshold slope (SS) is the measure used to indicate this property. For instance, a smaller SS means the transistor can be turned on using a smaller supply voltage while meeting the same off current. For MOSFETs, the SS has to be greater than ln(10) × kT/q where k is the Boltzmann constant, T is the absolute temperature, and q is the electron charge. This fundamental constraint arises from the thermionic nature of the MOSFET conduction mechanism and leads to a fundamental power/performance tradeoff, which could be overcome if SS values significantly lower than the theoretical 60-mV/decade limit could be achieved. Many device types have been proposed that could produce steep SS values, including tunneling field-effect transistors (TFETs), nanoelectromechanical system (NEMS) devices, ferroelectric-gate FETs, and impact ionization MOSFETs. Several recent papers have reported experimental observation of SS values in TFETs as low as 40 mV/decade at room temperature. These so-called “steep” devices’ main limitations are their low mobility, asymmetric drive current, bias dependent SS, and larger statistical variations in comparison to traditional MOSFETs.

Spin devices: Spintronics is a technology that utilizes nano magnets’ spin direction as the state variable. Spintronics has unique properties over CMOS, including nonvolatility, lower device count, and the potential for non-Boolean computing architectures. Spintronics devices’ nonvolatility enables instant processor wake-up and power-down that could dramatically reduce the static power consumption. Furthermore, it can enable novel processor-in-memory or logic-in-memory architectures that are not possible with silicon technology. Although in its infancy, research in spintronics has been gaining momentum over the past decade, as these devices could potentially overcome the power bottleneck of CMOS scaling by offering a completely new computing paradigm. In recent years, progress has been made toward demonstration of various post-CMOS spintronic devices including all-spin logic, spin wave devices, domain wall magnets for logic applications, and spin transfer torque magnetoresistive RAM (STT-MRAM) and spin-Hall torque (SHT) MRAM for memory applications. However, for spintronics technology to become a viable post-CMOS device platform, researchers must find ways to eliminate the transistors required to drive the clock and power supply signals. Otherwise, the performance will always be limited by CMOS technology. Other remaining challenges for spintronics devices include their relatively high active power, short interconnect distance, and complex fabrication process.

Flexible electronics: Distributed large area (cm2-to-m2) electronic systems based on flexible thin-film-transistor (TFT) technology are drawing much attention due to unique properties such as mechanical conformability, low temperature processability, large area coverage, and low fabrication costs. Various forms of flexible TFTs can either enable applications that were not achievable using traditional silicon based technology, or surpass them in terms of cost per area. Flexible electronics cannot match the performance of silicon-based ICs due to the low carrier mobility. Instead, this technology is meant to complement them by enabling distributed sensor systems over a large area with moderate performance (less than 1 MHz). Development of inkjet or roll-to-roll printing techniques for flexible TFTs is underway for low-cost manufacturing, making product-level implementations feasible. Despite these encouraging new developments, the low mobility and high sensitivity to processing parameters present major fabrication challenges for realizing flexible electronic systems.

CMOS scaling is coming to an end, but no single technology has emerged as a clear successor to silicon. The urgent need for post-CMOS alternatives will continue to drive high-risk, high-payoff research on novel device technologies. Replicating silicon’s success might sound like a pipe dream. But with the world’s best and brightest minds at work, we have reasons to be optimistic.

Author’s Note: I’d like to acknowledge the work of PhD students Ayan Paul and Jongyeon Kim.

Programme to train engineers for the VLSI segment to be launched V. SRIDHAR

The burgeoning bill for electronics imports and the government’s recent efforts to establish indigenous capacities for semiconductor manufacturing may be a step in the right direction, but the industry complains that the shortage of skilled manpower is still a major worry.

In an effort to bridge the gap, the Institute of Electrical and Electronics Engineers (IEEE) will start a unique course for engineers trying to enter the Very-Large-Scale Integration (VLSI) segment of the industry, the basic element in electronics.

VLSI is the process of manufacturing integrated circuits by combining thousands of transistors in a single chip. VLSI came into being in the 1970s when complex semiconductor and communication technologies were being developed. The microprocessor is an example of a VLSI device.

Collaborative effort

The Indian arm of the IEEE, a not-for-profit organisation based in New York, has entered into a collaboration with the R.V.-VLSI Design Centre, a unit of the Rashtreeya Shiksana Samiti Trust, which manages 28 educational institutions.

David Goldstein, director, New Product Development, IEEE, said the “blended learning” programme was designed by the R.V. College of Engineering, but the course content was “designed and validated by educational and industry experts from all over the world”. The IEEE had reviewed the programme, which included an online learning component and work in the laboratory.

Mr. Goldstein said the choice of location was critically dependent on not only the availability of lab facilities but also the availability of Electronic Design Automation tools, a category of software tools used for designing electronic systems such as printed circuit boards and integrated circuits. The tools would also be “vendor-neutral”, he said.

The existing cluster of VLSI designing companies in Bangalore was the reason Bangalore had been chosen as the launch pad for the initiative, Mr. Goldstein said.

“We are seeding this in Bangalore because we were satisfied by the quality of the laboratory facilities that were available at R.V. College, he said. The course is likely to be launched between April and June.

Mr. Goldstein said the programme targeted three sets of students: undergraduates, postgraduates and industry professionals. He said the professionals would go through “advanced domain modules, which is more appropriate to the skills that they already have”. In the first year, the programme would not offer certification. “Certification will happen in due course, but for now, we only plan to validate the programme so that there is acceptance in the industry,” he explained.

Increasing demand

At present, there were around 35,000 VLSI engineers in India, and the demand was increasing at an annual rate of about 10 per cent, Mr. Goldtsein said. The IEEE, he said, had plans to not only extend the programme to Mumbai, Hyderabad, Chennai and the National Capital Region, but to use India as a launch pad to expand overseas to Sri Lanka, Vietnam and other countries in South-east Asia.

“But we are now moving in a calibrated manner because we have to ensure that the facilities are available before we launch in other locations,” he said. Although he did not reveal the cost of the course, he said they would be “cost effective” and follow what the IEEE called the “emerging markets pricing schedule”.

Sponsorship by companies had the potential to reduce costs further, he said.

Intake

The intake was likely to be limited to 500 students, said Venkatesh Prasad, CEO of the design centre, even though this could be extended to 1,000 students soon. He said the constraint on intake was set by the availability of the “sophisticated tools” that were necessary for such a programme, the access to nanotech fabrication units, and access to people from the industry.

The campus was being established at Jayanagar because it was close to the electronics cluster in Electronics City, he said.

Keywords: IEEE, VLSI

Source: http://www.thehindu.com/sci-tech/technology/programme-to-train-engineers-for-the-vlsi-segment-to-be-launched/article5546069.ece

VLSI sector to generate 75K jobs by 2015

The very large-scale integration (VLSI) chip designing segment will generate 75,000 job opportunities in India by 2015, according to JA Chowdary, president, Hyderabad chapter of The Indus Entrepreneurs (TiE).

“About 25,000 people are currently employed in the VLSI designing industry in the country. With rapid growth expected in the coming few years, the segment will employ 75,000 people by 2015,” Chowdary told mediapersons at the three-day 25th International Conference on VLSI Design and the 11th International Conference on Embedded Systems, which kicked off in Hyderabad on Monday.

Dasaradha R Gude, convener of the conference, said: “Embedded systems market, which is one of the key drivers of Indian research and development (R&D) offshoring and is currently pegged at around $25 billion globally, is growing at a compounded annual growth rate (CAGR) of 16 per cent”.

As many as 50 eminent speakers are delivering lectures at the silver jubilee conference with the theme ‘Embedded Solutions for Emerging Markets – Consumer, Energy, Automotive’, in which 450 delegates from around the world are participating.

Long-term trends for the semiconductor industry and electronics are robust, driven by engineering excellence and creativity, according to Jaswinder S Ahuja, corporate vice-president and managing director of Cadence Design Systems in India.

Delivering his keynote at the conference, Ahuja said with ‘killer apps’ driving innovation, mobility will become the norm. “Today, apps drive the industry. This trend is here to stay,” he said, adding that systems companies would now require semiconductor companies to deliver application-driven hardware-software platforms.

Source: http://www.business-standard.com/article/companies/vlsi-sector-to-generate-75k-jobs-by-2015-112011000091_1.html