AEE Boosts Efficiency for Lower-Output-Voltage Step-Down Converters

Source: http://electronicdesign.com/power/aee-boosts-efficiency-lower-output-voltage-step-down-converters

A common challenge faced by every power-supply designer is the ability to achieve high-efficiency targets with lower-output-voltage step-down converters. For example, a 3.3-V output-voltage power supply may provide 91% efficiency at its full load, whereas a 1.8-V version may provide only 84% at full load. This decrease in efficiency produces higher operating temperatures than otherwise would be possible. And for portable systems, it wastes too much battery power. The hotter operating temperatures or shorter battery run times are clearly not desired by those using tablets, servers, or solid-state drives (SSDs) that contain these power supplies.

A new power-conversion approach is needed to keep efficiency high, regardless of the output voltage. One such method, automatic efficiency enhancement (AEE), provides higher efficiency with lower output voltages in these types of systems.

Why Does Efficiency Drop?

The efficiency drop for lower output voltages relates directly to the decreased amount of output power without a corresponding decrease in power loss. In a step-down converter, the losses are grouped into switching losses and conduction losses. Switching losses mostly depend on the input voltage, output current, and switching frequency. Conduction losses mostly depend on the output current and MOSFET resistances. Since the output voltage isn’t a strong contributor to the amount of loss, the losses don’t decrease as much as the output power.

Lower output voltages mean less output power, which is output current multiplied by the output voltage. Since efficiency is defined as output power divided by the output power plus the losses, lower efficiency results from the lower output power—but with the same losses.

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As an example, a 3.3-V output-voltage power supply delivering 6 A of output current with 2 W of loss produces 91% efficiency. The same power supply configured for a 1.8-V output voltage generates about the same 2 W of loss. This results in 84% efficiency due to the reduced output power. When configured for a 0.9-V output voltage, this 2 W of loss yields just 73% efficiency. Because the switching frequency, MOSFET resistances, output current, and input voltage are held constant in this comparison, losses are roughly the same, with 7% and 18% lower-efficiency results, respectively.

Two Higher-Efficiency Solutions

Input voltage and output current are defined by the system and load; thus, they’re not easily changeable. Power-supply designers need to either lower the switching frequency or adjust the MOSFET resistances to obtain higher efficiency for lower output voltages.

Usually, it’s impossible for power-supply designers to adjust the resistance values, because both high- and low-side MOSFETs are integrated inside most modern step-down converters. While it may be possible to have multiple step-down converter integrated circuits (ICs) available for use—each optimized for a specific output voltage—this isn’t generally practical from an IC design perspective. As a result, it’s typically not present in the market. It also creates more ICs in the bill of materials (BOM), which complicates the system design.

Lowering the switching frequency reduces the switching losses and increases efficiency. In many integrated step-down converters, it’s possible to adjust the frequency. However, adjusting the switching frequency usually necessitates a recalculation of the output filter and loop-compensation circuitry. This requires more design effort and time, and probably different components for different output-voltage circuits in the system. And that, once again, increases BOM count.

Intelligently Adjust Switching Frequency with AEE

Without any designer intervention, AEE adjusts the switching frequency to increase efficiency while using the same output filter and loop compensation. The switching frequency is automatically adjusted, based on the input voltage and output voltage, to maximize efficiency while maintaining control-loop stability and output-filter effectiveness. The frequency needn’t be set at a specific operating point optimized only for certain operating conditions; it dynamically adjusts itself during operation. Figure 1 shows the switching frequency for 3.3-, 1.8-, and 0.9-V output-voltage circuits running at 6 A of load current across a 6- to 15-V input-voltage range.

1. A two-phase step-down converter, such as the TPS62180, uses AEE to adjust the switching frequency based on input voltage and output voltage.

For lower output voltages, the switching frequency is reduced to maintain an appropriate amount of ripple current in the inductor. In the more common peak-current-limit type of step-down converter IC, the peak inductor current defines the IC’s available output current.

With the fixed level of the current limit set inside the IC, the peak inductor current must remain below the current-limit level at the full output current. Since the peak inductor current is the output current plus half of the inductor ripple current, the ripple current must be maintained at a low enough level. Otherwise, current limit is reached too soon and the IC is unable to provide the necessary output current.

With lower output voltages, the inductor ripple current is already reduced through Equation 1:

ΔI_L = V_OUT × (1 – V_OUT/V_IN)/(L × F_SW)                                  (1)

Because of this reduction, the switching frequency is also reduced with lower output voltages, increasing the ripple current back toward its allowed level. Figure 2 depicts the inductor ripple current calculated from the frequency data in Figure 1 and Equation 1.

2. AEE provides a constant ripple current at a given input voltage for any output voltage.

At a given operating point, the ripple current is essentially the same, regardless of the output voltage. AEE achieves this by reducing the switching frequency at the lower output voltages. Such a reduction narrows the gap in efficiency that occurs with decreasing output voltage. Figure 3 shows the efficiency when implementing AEE.

3. A two-phase step-down converter narrows the efficiency gap at lower output voltages through AEE.

Because the lower frequency at lower output voltages reduces switching losses, it also reduces total loss. This increases efficiency as opposed to most power-conversion topologies, which maintain a constant frequency for all output voltages.

Download this article in .PDF format This file type includes high resolution graphics and schematics when applicable.

Conclusion

In step-down converters such as the TPS62180, AEE provides higher efficiency than fixed-frequency, step-down converter topologies for lower output voltages. With AEE, 91% efficiency for a 3.3-V output voltage is maintained at a high level for lower output voltages: 87.5% for a 1.8-V output voltage and 82% for a 0.9-V output voltage. Such efficiencies represent a 3.5% and 9% increase, respectively, compared to fixed-frequency topologies. These efficiency increases are greatly valued in portable devices such as tablets, as well as thermally sensitive devices like SSDs and servers.

Modern ASIC Design Trends

Source: http://www.radio-electronics.com/articles/circuit-design/modern-asic-design-trends-107

Over the last decade many OEMs covering a broad cross section of different industry sectors have made clear their intention to gradually move away from the use of application specific integrated circuits (ASICs).

Instead they will rely more heavily on standard off-the-shelf components.

The reasoning behind this was primarily that it would allow them to push down overall costs and reduce their engineering resource.

However, in reality this has rarely happened, as within the last 3 to 4 years many of these companies have actually bolstered their design teams and continued to follow a predominantly ASIC centric approach to their system designs, so that they can maintain utmost differentiation from their rivals in increasingly competitive markets. Nevertheless it is evident that the ASIC landscape is going through a dramatic transformation and OEMs must respond to this accordingly.

ASIC considerations

There are various factors that need to be considered when undertaking ASIC implementation in order to ensure that the system design into which the chip is incorporated is as effective as possible, while the associated costs and the development time are both kept to a minimum. Over the course of the following article, these will be discussed.

Generally speaking, the key parameters involved in any ASIC implementation are performance, power, chip size, unit cost, functionality, non-recurring engineering (NRE) charges and time-to-market considerations.

There are a multitude of different trade-offs that can be made to designs in order to augment it for one (or more) of these parameters, but clearly if a customer wishes to witness a boost in a certain aspect of the ASIC’s characteristics it will come through making sacrifices elsewhere.

For example, in a portable consumer design it will be considered highly advantageous to keep the ASIC’s power consumption as low as possible, so that the end product’s battery life can be extended. It is also likely that there will be space constraints to take into account too. If these two demands are to be adequately met, then some compromises on the breadth of features that can be supported or the speed at which the ASIC can operate are likely to be needed.

FPGAs vs ASICs

Though programmable logic has been pitched as a substitute for standard cell technology, in reality FPGAs can’t deliver what ASICs can.

They have flexibility in terms of making changes to the design either during the development process providing the capability for early prototyping of the hardware or a development tool for software to reduce risk, or at a later stage when the end product needs revamping, but when it comes to the sort of optimization that is possible for an ASIC they can’t compete.

If an engineer bases their design on any FPGA series then they will be subject to restrictions in terms of the dimensions of the different chips in that series, the number of look-up tables (LUTs) that are available, etc..

With an ASIC it is entirely different - the system designer effectively has a blank canvas. There is far more scope when it comes to parameters like board space utilization, power budget, operating speed – all that has to be decided upon is which of these are the highest priority. In many cases, of course, system designers will want all of them at once.

This is why consultation is paramount. In the past ASIC design and implementation was undertaken with very little dialogue between the system designer and those doing the work. The complexity of the design, the more acute time and cost constraints, plus the performance demands involved mean that this is no longer advisable.

There should be detailed discussion between the parties concerned at the earliest stages. This would include a discussion of process technology choice that will have a large impact on the scope of the ASIC development and the functionality that is possible to implement. This will mean that customers are aware of what is achievable and their expectations can be kept under control - as a result the project can be completed on schedule and costly re-spins can be avoided.

Standard interconnects

In many cases system designers are addressing the issues now affecting ASIC implementation by employing standards to define their systems interconnect, processor subsystems and external interfaces.

There are popular processors and subsystems that share a common interconnect bus - thereby enabling code portability from one device to the next. IP blocks that are compliant with high speed interconnect protocols with verifiable standards (such as PCI Express, Ethernet or MIPI) allow the system designer to utilize the standard physical interface and controller blocks and know that compatibility will not be an issue once the ASIC is produced.

Many high bandwidth memory interface standards are also available along with silicon-proven interfaces that can be leveraged within the design. The application of these standards facilitates the reuse of proven IP blocks in ASIC designs and thereby mitigates the risk of errors arising that will impinge on the project, either technically or financially speaking.

Often customers will overestimate what they need from the ASIC design. They will ask for inclusion of high performance processor cores (such an ARM Cortex A family and PowerPC 460) or high speed serial interface (such as USB 3.0), when in fact by being slightly less ambitious with regard to the spec, an ASIC that is more than adequate can be realized with the shortened development times or less acute NRE expense.

Today’s system architects and designers are left with some difficult choices to make. Conventional thinking says that they can either decide to do all of the implementation work and manage the manufacturing, assembly and test flows themselves or alternatively they can engage with small design houses and foundries to meet their system requirements.

ASIC design flow

Though the latter means that some of the activities involved can be offloaded, in reality there still a definite need for the system designer to oversee the design flow, as well as the packaging and testing, since any hitch here could mean that the investment is wasted.

An alternative to either engaging with a design house and foundry combination or attempting to carry out the work using its own engineering staff is for the OEM to partner with a semiconductor manufacturer/vendor which has an established ASIC business.

Though the number of semiconductor companies doing so has become more limited in recent times, there are still companies that offer comprehensive ASIC implementation services. Following this route allows the OEM to benefit from the manufacturer/vendor’s experience of working with different processes, so that the best fit for a particular set of application requirements can be selected, as well as knowing which particular IP blocks work well together so that overall system performance is heightened.

For example, for previous design projects it may have been ascertained that some MAC and PHY IP block permutations are very successful when adding interconnect functionality to an ASIC design using a certain process technology. Furthermore, though ASICs offer a higher degree of application security than alternative IC solutions there is increasing anxiety throughout the industry about counterfeiting. It is therefore critical that OEMs are aware of the commercial impact that this can potentially have. This adds to the impetus for them to liaise with a company that has the capacity to safeguard against such problems.

Summary

A variety of business-related and technology-related pressures have driven a major shift in the strategies taken by OEMs when embarking on new system designs that employ ASICs. ON Semiconductor is well positioned to address the changing face of the ASIC market. It provides its customer base with ASIC implementation services and semiconductor manufacturing expertise using a mix of advanced technologies from its own fabs and those of its associated foundry partners. The company also has the capacity to offer clients access to its team of highly proficient IP experts, so that system designers are able to make informed decisions when it comes to dealing with the trade-offs based on performance, power, cost, functionality, etc. that will mean their systems are fully optimized for the particular task they are being designed to execute.

Practical PCB Design using DesignSpark PCB

Source: http://www.radio-electronics.com/articles/circuit-design/practical-pcb-design-using-designspark-pcb-143

DesignSpark PCB is RS Components' PCB design tool, part of a suite of applications intended to support rapid prototyping across both mechanical and electronics design.

DesignSpark PCB was released in 2010 following a partnership with Number One Systems, the creators of the Easy-PC CAD program (which unsurprisingly shares a number of similarities with DesignSpark PCB.)

RS Components has built up a thriving on-line community, with great tutorials and a lot of activity - not surprising, as RS is a well-known and respected worldwide organisation, and has put some effort into publicising the package.

The tool is provided free of charge, even for commercial use.

DesignSpark PCB basics

Being free, the engineer is not hampered by tightly controlled licence conditions, limiting the number of PCs to which the program can be installed. It does, however, require a connection to the Internet, which can be annoying, and caught the author out once while writing this review.

Despite being free RS claims it to be a full, professional program enabling the creation of multiple schematic pages, an unlimited PCB area and manufacturing data generation. What's going to be interesting, however, is how easy it is to learn. The author has used several CAD packages over the years, is not a professional PCB designer, and has not used this application before.

We are going to look at using Design Spark PCB to create a simple USB interface for foot operated switch, enabling a tap of the foot to trigger a series of keyboard commands, to an EPROM programmer application in our case. We will ignore the software design, although consideration is given for ease of development when choosing the microcontroller.

Let's roll a few requirements, and make some design decisions to simplify the design.

We want two inputs that will connect to momentary push to make switches. At the other end, we provide a type B USB socket for connection to a PC. We will select a microcontroller that is available in a DIL package, has a good free USB stack, and a free software development tool chain. We will use USB Full Speed mode since this has a very low data rate (12Mb/s), which will not require any special high frequency PCB tracking.

Our favourite microcontroller for this kind of work is Microchip's PIC18F2550-I/SP. It is supported by a great development IDE, free USB stack, and compiler.

The whole design will utilise through-hole components. We only need to manufacture a few boards and we don't anticipate a complex design, so soldering the components by hand will not be an issue. We save on the cost of a solder stencil and should be able to get the boards quicker (or even etch them in-house.)

The foot switch - not really relevant to the design of the PCB - was quickly located on the RS website through a search for "foot switch". We are going to provision the board with two inputs, one for each switch.

Installation

The installation application can be downloaded from the RS website at http://www.rs-online.com/designspark/electronics/

Only modern Windows OSs are supported; if you use Linux or MAC, you will need to run it with Wine or in a Windows virtual machine. Installation was straightforward (once we discovered you have to run the installer in Administrator mode,) but to complete the process 'activation' was required. This involved registering an account on the DesignSpark forum, and supplying a valid email address. RS is transparent about sending "appropriate marketing material" to your email address. It's very low volume, however.

DesignSpark PCB in use

On running DesignSpark for the first time we are presented with a Start page showing a few adverts. There is no design canvas visible, but this is reasonable, as we should really be setting up a project at this stage. Sure enough, selecting File->New brings up a dialog and we can enter the name for the project, and then create a schematic. At this point we have a dialog as shown in Figure 1. Specialised components can be discovered through ModelSource, an on-line database of selected RS components, or picked from a library of generic devices.

Figure 1: Starting schematic capture, loading a microcontroller from ModelSource. Inset: All manner of files can be included in the project; here, we have a photograph of the original notebook design attached as a jpeg file

Our initial schematic design was sketched out in a logbook and then photographed, downloaded to the PC and imported as a support design file. In this manner all of your notes can be kept with your CAD design in a single project. Creating the schematic - remember, this was our first experience with DesignSpark - was straightforward and took 30 minutes. We even dropped in a few extra I/O pins on headers for future proofing. You can see the results in Figure 2.

Figure 2: Completed schematic. Notice we couldn't help adding some additional inputs, for future proofing

It's great that ModelSource provides access to online datasheet material from a single click of the mouse, accelerating the selection of appropriate specialised parts from the ones available in the program.

Converting the DesignSpark schematic to a board

Satisfied with the schematic, we select Tools->Translate To PCB... to create the board design. At first we are presented with a PCB Wizard dialog that appears to suggest we will be hand held though the process.

First, we select the type of board we are targeting - single sided, the default double sided (our choice,) and so on. This is more intuitive than the common technique of letting us manage dozens of layers ourselves. Next we have the option to refine the list of layers - we accept the defaults. Then we define the board dimensions. We leave this at default, as the board outline can be adjusted as the components are arranged and signals routed.

Finally we have the option to have the components placed automatically, and the signals routed. Automated placement is rarely successful and today was no exception, so we backed the changed out and opted for component placement around the board periphery, for manual placement.

Moving components was just as intuitive as creating the schematic. A particularly welcome feature was that design rule checks were performed dynamically as you moved parts around, and the airwires - lines that indicated connectively between parts - are also recalculated. This stops you making layout mistakes that would otherwise be picked up later on.

Thirty minutes later and we are happy with the component placement, so it's time to route the signals. The auto-router's first attempt was poor, so we manually routed the critical signals - USB and power - and then let the auto router finish the rest. It did a fair job.

Creating the copper flood fill and then generating the Gerber format files was again intuitive, and quick. Going from Figure 3 to Figure 4 took just over an hour.

Figure 3: Initial board layout

Figure 4: Completed board layout, in 3D view

Conclusions

The learning curve for someone with a little previous CAD experience was negligible. Its capabilities would suit many SMEs (it's the primary tool for the author's company) and engineers will be productive with the tool after just a few hours.

Its limitation is the size of the library although, to be fair, you will always be spending time validating and tweaking your libraries.

With its free licence and unlimited capabilities it's a difficult tool to beat.