AEE Boosts Efficiency for Lower-Output-Voltage Step-Down Converters

Source: http://electronicdesign.com/power/aee-boosts-efficiency-lower-output-voltage-step-down-converters

A common challenge faced by every power-supply designer is the ability to achieve high-efficiency targets with lower-output-voltage step-down converters. For example, a 3.3-V output-voltage power supply may provide 91% efficiency at its full load, whereas a 1.8-V version may provide only 84% at full load. This decrease in efficiency produces higher operating temperatures than otherwise would be possible. And for portable systems, it wastes too much battery power. The hotter operating temperatures or shorter battery run times are clearly not desired by those using tablets, servers, or solid-state drives (SSDs) that contain these power supplies.

A new power-conversion approach is needed to keep efficiency high, regardless of the output voltage. One such method, automatic efficiency enhancement (AEE), provides higher efficiency with lower output voltages in these types of systems.

Why Does Efficiency Drop?

The efficiency drop for lower output voltages relates directly to the decreased amount of output power without a corresponding decrease in power loss. In a step-down converter, the losses are grouped into switching losses and conduction losses. Switching losses mostly depend on the input voltage, output current, and switching frequency. Conduction losses mostly depend on the output current and MOSFET resistances. Since the output voltage isn’t a strong contributor to the amount of loss, the losses don’t decrease as much as the output power.

Lower output voltages mean less output power, which is output current multiplied by the output voltage. Since efficiency is defined as output power divided by the output power plus the losses, lower efficiency results from the lower output power—but with the same losses.

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As an example, a 3.3-V output-voltage power supply delivering 6 A of output current with 2 W of loss produces 91% efficiency. The same power supply configured for a 1.8-V output voltage generates about the same 2 W of loss. This results in 84% efficiency due to the reduced output power. When configured for a 0.9-V output voltage, this 2 W of loss yields just 73% efficiency. Because the switching frequency, MOSFET resistances, output current, and input voltage are held constant in this comparison, losses are roughly the same, with 7% and 18% lower-efficiency results, respectively.

Two Higher-Efficiency Solutions

Input voltage and output current are defined by the system and load; thus, they’re not easily changeable. Power-supply designers need to either lower the switching frequency or adjust the MOSFET resistances to obtain higher efficiency for lower output voltages.

Usually, it’s impossible for power-supply designers to adjust the resistance values, because both high- and low-side MOSFETs are integrated inside most modern step-down converters. While it may be possible to have multiple step-down converter integrated circuits (ICs) available for use—each optimized for a specific output voltage—this isn’t generally practical from an IC design perspective. As a result, it’s typically not present in the market. It also creates more ICs in the bill of materials (BOM), which complicates the system design.

Lowering the switching frequency reduces the switching losses and increases efficiency. In many integrated step-down converters, it’s possible to adjust the frequency. However, adjusting the switching frequency usually necessitates a recalculation of the output filter and loop-compensation circuitry. This requires more design effort and time, and probably different components for different output-voltage circuits in the system. And that, once again, increases BOM count.

Intelligently Adjust Switching Frequency with AEE

Without any designer intervention, AEE adjusts the switching frequency to increase efficiency while using the same output filter and loop compensation. The switching frequency is automatically adjusted, based on the input voltage and output voltage, to maximize efficiency while maintaining control-loop stability and output-filter effectiveness. The frequency needn’t be set at a specific operating point optimized only for certain operating conditions; it dynamically adjusts itself during operation. Figure 1 shows the switching frequency for 3.3-, 1.8-, and 0.9-V output-voltage circuits running at 6 A of load current across a 6- to 15-V input-voltage range.

1. A two-phase step-down converter, such as the TPS62180, uses AEE to adjust the switching frequency based on input voltage and output voltage.

For lower output voltages, the switching frequency is reduced to maintain an appropriate amount of ripple current in the inductor. In the more common peak-current-limit type of step-down converter IC, the peak inductor current defines the IC’s available output current.

With the fixed level of the current limit set inside the IC, the peak inductor current must remain below the current-limit level at the full output current. Since the peak inductor current is the output current plus half of the inductor ripple current, the ripple current must be maintained at a low enough level. Otherwise, current limit is reached too soon and the IC is unable to provide the necessary output current.

With lower output voltages, the inductor ripple current is already reduced through Equation 1:

ΔI_L = V_OUT × (1 – V_OUT/V_IN)/(L × F_SW)                                  (1)

Because of this reduction, the switching frequency is also reduced with lower output voltages, increasing the ripple current back toward its allowed level. Figure 2 depicts the inductor ripple current calculated from the frequency data in Figure 1 and Equation 1.

2. AEE provides a constant ripple current at a given input voltage for any output voltage.

At a given operating point, the ripple current is essentially the same, regardless of the output voltage. AEE achieves this by reducing the switching frequency at the lower output voltages. Such a reduction narrows the gap in efficiency that occurs with decreasing output voltage. Figure 3 shows the efficiency when implementing AEE.

3. A two-phase step-down converter narrows the efficiency gap at lower output voltages through AEE.

Because the lower frequency at lower output voltages reduces switching losses, it also reduces total loss. This increases efficiency as opposed to most power-conversion topologies, which maintain a constant frequency for all output voltages.

Download this article in .PDF format This file type includes high resolution graphics and schematics when applicable.

Conclusion

In step-down converters such as the TPS62180, AEE provides higher efficiency than fixed-frequency, step-down converter topologies for lower output voltages. With AEE, 91% efficiency for a 3.3-V output voltage is maintained at a high level for lower output voltages: 87.5% for a 1.8-V output voltage and 82% for a 0.9-V output voltage. Such efficiencies represent a 3.5% and 9% increase, respectively, compared to fixed-frequency topologies. These efficiency increases are greatly valued in portable devices such as tablets, as well as thermally sensitive devices like SSDs and servers.

Modern ASIC Design Trends

Source: http://www.radio-electronics.com/articles/circuit-design/modern-asic-design-trends-107

Over the last decade many OEMs covering a broad cross section of different industry sectors have made clear their intention to gradually move away from the use of application specific integrated circuits (ASICs).

Instead they will rely more heavily on standard off-the-shelf components.

The reasoning behind this was primarily that it would allow them to push down overall costs and reduce their engineering resource.

However, in reality this has rarely happened, as within the last 3 to 4 years many of these companies have actually bolstered their design teams and continued to follow a predominantly ASIC centric approach to their system designs, so that they can maintain utmost differentiation from their rivals in increasingly competitive markets. Nevertheless it is evident that the ASIC landscape is going through a dramatic transformation and OEMs must respond to this accordingly.

ASIC considerations

There are various factors that need to be considered when undertaking ASIC implementation in order to ensure that the system design into which the chip is incorporated is as effective as possible, while the associated costs and the development time are both kept to a minimum. Over the course of the following article, these will be discussed.

Generally speaking, the key parameters involved in any ASIC implementation are performance, power, chip size, unit cost, functionality, non-recurring engineering (NRE) charges and time-to-market considerations.

There are a multitude of different trade-offs that can be made to designs in order to augment it for one (or more) of these parameters, but clearly if a customer wishes to witness a boost in a certain aspect of the ASIC’s characteristics it will come through making sacrifices elsewhere.

For example, in a portable consumer design it will be considered highly advantageous to keep the ASIC’s power consumption as low as possible, so that the end product’s battery life can be extended. It is also likely that there will be space constraints to take into account too. If these two demands are to be adequately met, then some compromises on the breadth of features that can be supported or the speed at which the ASIC can operate are likely to be needed.

FPGAs vs ASICs

Though programmable logic has been pitched as a substitute for standard cell technology, in reality FPGAs can’t deliver what ASICs can.

They have flexibility in terms of making changes to the design either during the development process providing the capability for early prototyping of the hardware or a development tool for software to reduce risk, or at a later stage when the end product needs revamping, but when it comes to the sort of optimization that is possible for an ASIC they can’t compete.

If an engineer bases their design on any FPGA series then they will be subject to restrictions in terms of the dimensions of the different chips in that series, the number of look-up tables (LUTs) that are available, etc..

With an ASIC it is entirely different - the system designer effectively has a blank canvas. There is far more scope when it comes to parameters like board space utilization, power budget, operating speed – all that has to be decided upon is which of these are the highest priority. In many cases, of course, system designers will want all of them at once.

This is why consultation is paramount. In the past ASIC design and implementation was undertaken with very little dialogue between the system designer and those doing the work. The complexity of the design, the more acute time and cost constraints, plus the performance demands involved mean that this is no longer advisable.

There should be detailed discussion between the parties concerned at the earliest stages. This would include a discussion of process technology choice that will have a large impact on the scope of the ASIC development and the functionality that is possible to implement. This will mean that customers are aware of what is achievable and their expectations can be kept under control - as a result the project can be completed on schedule and costly re-spins can be avoided.

Standard interconnects

In many cases system designers are addressing the issues now affecting ASIC implementation by employing standards to define their systems interconnect, processor subsystems and external interfaces.

There are popular processors and subsystems that share a common interconnect bus - thereby enabling code portability from one device to the next. IP blocks that are compliant with high speed interconnect protocols with verifiable standards (such as PCI Express, Ethernet or MIPI) allow the system designer to utilize the standard physical interface and controller blocks and know that compatibility will not be an issue once the ASIC is produced.

Many high bandwidth memory interface standards are also available along with silicon-proven interfaces that can be leveraged within the design. The application of these standards facilitates the reuse of proven IP blocks in ASIC designs and thereby mitigates the risk of errors arising that will impinge on the project, either technically or financially speaking.

Often customers will overestimate what they need from the ASIC design. They will ask for inclusion of high performance processor cores (such an ARM Cortex A family and PowerPC 460) or high speed serial interface (such as USB 3.0), when in fact by being slightly less ambitious with regard to the spec, an ASIC that is more than adequate can be realized with the shortened development times or less acute NRE expense.

Today’s system architects and designers are left with some difficult choices to make. Conventional thinking says that they can either decide to do all of the implementation work and manage the manufacturing, assembly and test flows themselves or alternatively they can engage with small design houses and foundries to meet their system requirements.

ASIC design flow

Though the latter means that some of the activities involved can be offloaded, in reality there still a definite need for the system designer to oversee the design flow, as well as the packaging and testing, since any hitch here could mean that the investment is wasted.

An alternative to either engaging with a design house and foundry combination or attempting to carry out the work using its own engineering staff is for the OEM to partner with a semiconductor manufacturer/vendor which has an established ASIC business.

Though the number of semiconductor companies doing so has become more limited in recent times, there are still companies that offer comprehensive ASIC implementation services. Following this route allows the OEM to benefit from the manufacturer/vendor’s experience of working with different processes, so that the best fit for a particular set of application requirements can be selected, as well as knowing which particular IP blocks work well together so that overall system performance is heightened.

For example, for previous design projects it may have been ascertained that some MAC and PHY IP block permutations are very successful when adding interconnect functionality to an ASIC design using a certain process technology. Furthermore, though ASICs offer a higher degree of application security than alternative IC solutions there is increasing anxiety throughout the industry about counterfeiting. It is therefore critical that OEMs are aware of the commercial impact that this can potentially have. This adds to the impetus for them to liaise with a company that has the capacity to safeguard against such problems.

Summary

A variety of business-related and technology-related pressures have driven a major shift in the strategies taken by OEMs when embarking on new system designs that employ ASICs. ON Semiconductor is well positioned to address the changing face of the ASIC market. It provides its customer base with ASIC implementation services and semiconductor manufacturing expertise using a mix of advanced technologies from its own fabs and those of its associated foundry partners. The company also has the capacity to offer clients access to its team of highly proficient IP experts, so that system designers are able to make informed decisions when it comes to dealing with the trade-offs based on performance, power, cost, functionality, etc. that will mean their systems are fully optimized for the particular task they are being designed to execute.

Practical PCB Design using DesignSpark PCB

Source: http://www.radio-electronics.com/articles/circuit-design/practical-pcb-design-using-designspark-pcb-143

DesignSpark PCB is RS Components' PCB design tool, part of a suite of applications intended to support rapid prototyping across both mechanical and electronics design.

DesignSpark PCB was released in 2010 following a partnership with Number One Systems, the creators of the Easy-PC CAD program (which unsurprisingly shares a number of similarities with DesignSpark PCB.)

RS Components has built up a thriving on-line community, with great tutorials and a lot of activity - not surprising, as RS is a well-known and respected worldwide organisation, and has put some effort into publicising the package.

The tool is provided free of charge, even for commercial use.

DesignSpark PCB basics

Being free, the engineer is not hampered by tightly controlled licence conditions, limiting the number of PCs to which the program can be installed. It does, however, require a connection to the Internet, which can be annoying, and caught the author out once while writing this review.

Despite being free RS claims it to be a full, professional program enabling the creation of multiple schematic pages, an unlimited PCB area and manufacturing data generation. What's going to be interesting, however, is how easy it is to learn. The author has used several CAD packages over the years, is not a professional PCB designer, and has not used this application before.

We are going to look at using Design Spark PCB to create a simple USB interface for foot operated switch, enabling a tap of the foot to trigger a series of keyboard commands, to an EPROM programmer application in our case. We will ignore the software design, although consideration is given for ease of development when choosing the microcontroller.

Let's roll a few requirements, and make some design decisions to simplify the design.

We want two inputs that will connect to momentary push to make switches. At the other end, we provide a type B USB socket for connection to a PC. We will select a microcontroller that is available in a DIL package, has a good free USB stack, and a free software development tool chain. We will use USB Full Speed mode since this has a very low data rate (12Mb/s), which will not require any special high frequency PCB tracking.

Our favourite microcontroller for this kind of work is Microchip's PIC18F2550-I/SP. It is supported by a great development IDE, free USB stack, and compiler.

The whole design will utilise through-hole components. We only need to manufacture a few boards and we don't anticipate a complex design, so soldering the components by hand will not be an issue. We save on the cost of a solder stencil and should be able to get the boards quicker (or even etch them in-house.)

The foot switch - not really relevant to the design of the PCB - was quickly located on the RS website through a search for "foot switch". We are going to provision the board with two inputs, one for each switch.

Installation

The installation application can be downloaded from the RS website at http://www.rs-online.com/designspark/electronics/

Only modern Windows OSs are supported; if you use Linux or MAC, you will need to run it with Wine or in a Windows virtual machine. Installation was straightforward (once we discovered you have to run the installer in Administrator mode,) but to complete the process 'activation' was required. This involved registering an account on the DesignSpark forum, and supplying a valid email address. RS is transparent about sending "appropriate marketing material" to your email address. It's very low volume, however.

DesignSpark PCB in use

On running DesignSpark for the first time we are presented with a Start page showing a few adverts. There is no design canvas visible, but this is reasonable, as we should really be setting up a project at this stage. Sure enough, selecting File->New brings up a dialog and we can enter the name for the project, and then create a schematic. At this point we have a dialog as shown in Figure 1. Specialised components can be discovered through ModelSource, an on-line database of selected RS components, or picked from a library of generic devices.

Figure 1: Starting schematic capture, loading a microcontroller from ModelSource. Inset: All manner of files can be included in the project; here, we have a photograph of the original notebook design attached as a jpeg file

Our initial schematic design was sketched out in a logbook and then photographed, downloaded to the PC and imported as a support design file. In this manner all of your notes can be kept with your CAD design in a single project. Creating the schematic - remember, this was our first experience with DesignSpark - was straightforward and took 30 minutes. We even dropped in a few extra I/O pins on headers for future proofing. You can see the results in Figure 2.

Figure 2: Completed schematic. Notice we couldn't help adding some additional inputs, for future proofing

It's great that ModelSource provides access to online datasheet material from a single click of the mouse, accelerating the selection of appropriate specialised parts from the ones available in the program.

Converting the DesignSpark schematic to a board

Satisfied with the schematic, we select Tools->Translate To PCB... to create the board design. At first we are presented with a PCB Wizard dialog that appears to suggest we will be hand held though the process.

First, we select the type of board we are targeting - single sided, the default double sided (our choice,) and so on. This is more intuitive than the common technique of letting us manage dozens of layers ourselves. Next we have the option to refine the list of layers - we accept the defaults. Then we define the board dimensions. We leave this at default, as the board outline can be adjusted as the components are arranged and signals routed.

Finally we have the option to have the components placed automatically, and the signals routed. Automated placement is rarely successful and today was no exception, so we backed the changed out and opted for component placement around the board periphery, for manual placement.

Moving components was just as intuitive as creating the schematic. A particularly welcome feature was that design rule checks were performed dynamically as you moved parts around, and the airwires - lines that indicated connectively between parts - are also recalculated. This stops you making layout mistakes that would otherwise be picked up later on.

Thirty minutes later and we are happy with the component placement, so it's time to route the signals. The auto-router's first attempt was poor, so we manually routed the critical signals - USB and power - and then let the auto router finish the rest. It did a fair job.

Creating the copper flood fill and then generating the Gerber format files was again intuitive, and quick. Going from Figure 3 to Figure 4 took just over an hour.

Figure 3: Initial board layout

Figure 4: Completed board layout, in 3D view

Conclusions

The learning curve for someone with a little previous CAD experience was negligible. Its capabilities would suit many SMEs (it's the primary tool for the author's company) and engineers will be productive with the tool after just a few hours.

Its limitation is the size of the library although, to be fair, you will always be spending time validating and tweaking your libraries.

With its free licence and unlimited capabilities it's a difficult tool to beat.

VHDL & Verilog Compared & Contrasted

VHDL & Verilog Compared & Contrasted
Plus Modeled Example Written in
VHDL, Verilog and C

Douglas J. Smith
VeriBest Incorporated
e-mail: djsmith@veribest.com
Source: http://www.angelfire.com/in/rajesh52/verilogvhdl.html

Abstract

This tutorial is in two parts. The first part takes an unbiased view of VHDL and Verilog by comparing their similarities and contrasting their differences. The second part contains a worked example of a model that computes the Greatest Common Divisor (GCD) of two numbers. The GCD is modeled at the algorithmic level in VHDL, Verilog and for comparison purposes, C. It is then shown modeled at the RTL in VHDL and Verilog.

1. Introduction

There are now two industry standard hardware description languages, VHDL and Verilog. The complexity of ASIC and FPGA designs has meant an increase in the number of specialist design consultants with specific tools and with their own libraries of macro and mega cells written in either VHDL or Verilog. As a result, it is important that designers know both VHDL and Verilog and that EDA tools vendors provide tools that provide an environment allowing both languages to be used in unison. For example, a designer might have a model of a PCI bus interface written in VHDL, but wants to use it in a design with macros written in Verilog.

2. Background

VHDL (Very high speed integrated circuit Hardware Description Language) became IEEE standard 1076 in 1987. It was updated in 1993 and is known today as "IEEE standard 1076 1993". The Verilog hardware description language has been used far longer than VHDL and has been used extensively since it was launched by Gateway in 1983. Cadence bought Gateway in 1989 and opened Verilog to the public domain in 1990. It became IEEE standard 1364 in December 1995.

There are two aspects to modeling hardware that any hardware description language facilitates; true abstract behavior and hardware structure. This means modeled hardware behavior is not prejudiced by structural or design aspects of hardware intent and that hardware structure is capable of being modeled irrespective of the design's behavior.

3. VHDL/Verilog compared & contrasted

This section compares and contrasts individual aspects of the two languages; they are listed in alphabetical order.

Capability

Hardware structure can be modeled equally effectively in both VHDL and Verilog. When modeling abstract hardware, the capability of VHDL can sometimes only be achieved in Verilog when using the PLI. The choice of which to use is not therefore based solely on technical capability but on:

• personal preferences
• EDA tool availability
• commercial, business and marketing issues

The modeling constructs of VHDL and Verilog cover a slightly different spectrum across the levels of behavioral abstraction; see Figure 1.

Figure 1. HDL modeling capability

Compilation

VHDL. Multiple design-units (entity/architecture pairs), that reside in the same system file, may be separately compiled if so desired. However, it is good design practice to keep each design unit in it's own system file in which case separate compilation should not be an issue.

Verilog. The Verilog language is still rooted in it's native interpretative mode. Compilation is a means of speeding up simulation, but has not changed the original nature of the language. As a result care must be taken with both the compilation order of code written in a single file and the compilation order of multiple files. Simulation results can change by simply changing the order of compilation.

Data types

VHDL. A multitude of language or user defined data types can be used. This may m ean dedicated conversion functions are needed to convert objects from one type to another. The choice of which data types to use should be considered wisely, especially enumerated (abstract) data types. This will make models easier to write, clearer to read and avoid unnecessary conversion functions that can clutter the code. VHDL may be preferred because it allows a multitude of language or user defined data types to be used.

Verilog. Compared to VHDL, Verilog data types a re very simple, easy to use and very much geared towards modeling hardware structure as opposed to abstract hardware modeling. Unlike VHDL, all data types used in a Verilog model are defined by the Verilog language and not by the user. There are net data types, for example wire, and a register data type called reg. A model with a signal whose type is one of the net data types has a corresponding electrical wire in the implied modeled circuit. Objects, that is signals, of type reg hold their value over simulation delta cycles and should not be confused with the modeling of a hardware register. Verilog may be preferred because of it's simplicity.

Design reusability

VHDL. Procedures and functions may be placed in a package so that they are avail able to any design-unit that wishes to use them.

Verilog. There is no concept of packages in Verilog. Functions and procedures used within a model must be defined in the module. To make functions and procedures generally accessible from different module statements the functions and procedures must be placed in a separate system file and included using the `include compiler directive.

Easiest to Learn

Starting with zero knowledge of either language, Verilog is probably the easiest to grasp and understand. This assumes the Verilog compiler directive language for simulation and the PLI language is not included. If these languages are included they can be looked upon as two additional languages that need to be learned. VHDL may seem less intuitive at first for two primary reasons. First, it is very strongly typed; a feature that makes it robust and powerful for the advanced user after a longer learning phase. Second, there are many ways to model the same circuit, specially those with large hierarchical structures.

Forward and back annotation

A spin-off from Verilog is the Standard Delay Format (SDF). This is a general purpose format used to define the timing delays in a circuit. The format provides a bidirectional link between, chip layout tools, and either synthesis or simulation tools, in order to provide more accurate timing representations. The SDF format is now an industry standard in it's own right.

High level constructs

VHDL. There are more constructs and features for high-level modeling in VHDL than there are in Verilog. Abstract data types can be used along with the following statements:

* package statements for model reuse,

* configuration statements for configuring design structure,

* generate statements for replicating structure,

* generic statements for generic models that can be individually characterized, for example, bit width.

All these language statements are useful in synthesizable models.

Verilog. Except for being able to parameterize models by overloading parameter constants, there is no equivalent to the high-level VHDL modeling statements in Verilog.

Language Extensions

The use of language extensions will make a model non standard and most likely not portable across other design tools. However, sometimes they are necessary in order to achieve the desired results.

VHDL. Has an attribute called 'foreign that allows architectures and subprograms to be modeled in another language.

Verilog. The Programming Language Interface (PLI) is an interface mechanism between Verilog models and Verilog software tools. For example, a designer, or more likely, a Verilog tool vendor, can specify user defined tasks or functions in the C programming language, and then call them from the Verilog source description. Use of such tasks or functions make a Verilog model nonstandard and so may not be usable by other Verilog tools. Their use is not recommended.

Libraries

VHDL. A library is a store for compiled entities, architectures, packages and configurations. Useful for managing multiple design projects.

Verilog. There is no concept of a library in Verilog. This is due to it's origins as an interpretive language.

Low Level Constructs

VHDL. Simple two input logical operators are built into the language, they are: NOT, AND, OR, NAND, NOR, XOR and XNOR. Any timing must be separately specified using the after clause. Separate constructs defined under the VITAL language must be used to define the cell primitives of ASIC and FPGA libraries.

Verilog. The Verilog language was originally developed with gate level modeling in mind, and so has very good constructs for modeling at this level and for modeling the cell primitives of ASIC and FPGA libraries. Examples include User Defined Primitive s (UDP), truth tables and the specify block for specifying timing delays across a module.

Managing large designs

VHDL. Configuration, generate, generic and package statements all help manage large design structures.

Verilog. There are no statements in Verilog that help manage large designs.

Operators

The majority of operators are the same between the two languages. Verilog does have very useful unary reduction operators that are not in VHDL. A loop statement can be used in VHDL to perform the same operation as a Verilog unary reduction operator. VHDL has the mod operator that is not found in Verilog.

Parameterizable models

VHDL. A specific bit width model can be instantiated from a generic n-bit model using the generic statement. The generic model will not synthesize until it is instantiated and the value of the generic given.

Verilog. A specific width model can be instantiated from a generic n-bit model using overloaded parameter values. The generic model must have a default parameter value defined. This means two things. In the absence of an overloaded value being specified, it will still synthesize, but will use the specified default parameter value. Also, it does not need to be instantiated with an overloaded parameter value specified, before it will synthesize.

Procedures and tasks

VHDL allows concurrent procedure calls; Verilog does not allow concurrent task calls.

Readability

This is more a matter of coding style and experience than language feature. VHDL is a concise and verbose language; its roots are based on Ada. Verilog is more like C because it's constructs are based approximately 50% on C and 50% on Ada. For this reason an existing C programmer may prefer Verilog over VHDL. Although an existing programmer of both C and Ada may find the mix of constructs somewhat confusing at first. Whatever HDL is used, when writing or reading an HDL model to be synthesized it is important to think about hardware intent.

Structural replication

VHDL. The generate statement replicates a number of instances of the same design-unit or some sub part of a design, and connects it appropriately.

Verilog. There is no equivalent to the generate statement in Verilog.

Test harnesses

Designers typically spend about 50% of their time writing synthesizable models and the other 50% writing a test harness to verify the synthesizable models. Test harnesses are not restricted to the synthesizable subset and so are free to use the full potential of the language. VHDL has generic and configuration statements that are useful in test harnesses, that are not found in Verilog.

Verboseness

VHDL. Because VHDL is a very strongly typed language models must be coded precisely with defined and matching data types. This may be considered an advantage or disadvantage. However, it does mean models are often more verbose, and the code often longer, than it's Verilog equivalent.

Verilog. Signals representing objects of different bits widths may be assigned to each other. The signal representing the smaller number of bits is automatically padded out to that of the larger number of bits, and is independent of whether it is the assigned signal or not. Unused bits will be automatically optimized away during the synthesis process. This has the advantage of not needing to model quite so explicitly as in VHDL, but does mean unintended modeling errors will not be identified by an analyzer.

4. Greatest Common Divisor

Models of a greatest common divisor circuit is posed as problem and solution exercise. A model written in C is included in addition to VHDL and Verilog for comparison purposes.

4.1 Problem

The problem consists of three parts:

a) Design three algorithmic level models of an algorithm that finds the Greatest Common Divisor (GCD) of two numbers in the software programming language, C, and the two hardware description languages, VHDL and Verilog. Use common test data files to test the algorithm where practically possible. Neither the VHDL nor Verilog models need contain timing. All three models should automatically indicate a pass or fail condition.

b) Model the GCD algorithm at the RTL level for synthesis in both VHDL and Verilog. The model must be generic so that it can be instantiated with different bit widths. A Load signal should indicate when input data is valid, and a signal cal led Done, should be provided to signify when valid output data is available. The generic model should be verified with 8-bit bus signals.

c) Write VHDL and Verilog test harnesses for the two models that: 1) use the same test data files used by the algorithmic level models, and 2), instantiates both the RTL and synthesized gate level models so that they are simulated and tested at the same time.

4.2 Solution

The solution is broken into three parts corresponding to those of the problem. The solution parts use the following combined test and reference data files.

file: gcd_test_data.txt                   file: gcd_test_data_hex.txt

  21    49    7           15    31    7      // Decimal     21    49    7

  25    30    5           19    1E    5      // Decimal     25    30    5

  19    27    1           13    1B    1      // Decimal     19    27    1

  40    40   40           28    28   28      // Decimal     40    40   40

 250   190   10           FA    6E    A      // Decimal    250   190   10

   5   250    5            5    FA    5      // Decimal      5   250    5

4.2.1 Designing algorithmic level models in C, VHDL and Verilog

The algorithm used to find the greatest common divisor between two numbers is shown in Figure 2.
Figure 2. GCD Algorithm It works by continually subtracting the smaller of the two numbers, A or B, from the largest until such point the smallest number becomes equal to zero. It does this by continually subtracting B from A while A is greater than B, and then s wapping A and B around when A becomes less than B so that the new value of B can once again be continually subtracted from A. This process continues until B becomes zero.

C algorithmic model

The C model first declares integer values for the two inputs A and B, the computed output of the algorithm Y, and the reference output Y_Ref. Integer Y_Ref is the expected GCD result and used to compare with the computed result from the algorithm. The integer Swap is also declared and used in the algorithm to swap the two inputs A and B. A final integer, Passed, is used to indicate a pass (1) or fail (0) condition.A file pointer (file_pointer) is defined in order to access the test data file "gcd_test_data.txt". It is opened for read mode only. Integer Passed is initially set to 1 and only set to 0 if the algorithm fails.
Reading test data file. The test data file contains three numbers on each line corresponding to values of A, B and Y_Ref respectively. A while loop is used to: 1) read each line of the test data file, 2) assign the three values to A, B and Y_Ref respectively, 3) use A and B to compute the GCD output Y, and 4) compare Y with Y_Ref. This while loop continues while there is test data in the test data file.
Algorithm implementation. The initial if statement is an extra check that both A and B are not zero. The algorithm is then modeled using two while statements. The first, outer-most, while statement checks to see if B has reached zero; if it has the GCD has been found. The second, inner-most, while statement checks to see if A is greater than or equal to B; if it is, it continually subtracts A from B and puts the result back in A. When A becomes less than B the inner most while loop completes, A and B are swapped using Swap, and the outer most while statement rechecks B to see if it has reached zero.
Testing the result. The algorithm is tested using an if statement which tests to see if the computed result Y is the same as the expected result Y_Ref. If they are different an error message is printed to the screen and Passed assigned the value 0. Finally, when all tests have completed and Passed is still equal to 1 a passed message is printed to the screen.

C algorithmic level model

#include <stdio.h>

main ()

   {

   int A_in, B_in, A, B, Swap, Y, Y_Ref, Passed;

   FILE *file_pointer;

   file_pointer = fopen("gcd_test_data.txt", "r");

   Passed = 1;

   while (!feof(file_pointer))

        {

         /*------------------------------------*/

         /* Read test data from file           */

         /*------------------------------------*/

         fscanf (file_pointer, "%d %d %d\n", &A_in, &B_in, &Y_Ref);

         /*----------------------------------*/

         /* Model GCD algorithm              */

         /*----------------------------------*/

         A = A_in;

         B = B_in;

         if (A != 0 && B != 0)

           {

            while (B != 0)

              {

               while (A >= B)

                  {

                   A = A - B;

                   }

               Swap = A;

               A = B;

               B = Swap;

               }

           }

         else

           {

            A = 0;

           }

         Y = A;

         /*------------------------------*/

         /* Test GCD algorithm           */

         /*------------------------------*/

         if (Y != Y_Ref)

           {

            printf ("Error. A=%d B=%d Y=%d Y_Ref= %d\n", A_in, B_in, Y, Y_Ref);

            Passed = 0;

           }

         }

       if (Passed = 1) printf ("GCD algorithm test passed ok\n");

    }

VHDL algorithmic level model

The VHDL model follows exactly the same principle as defined for the C model. When reading the integer values from the test date file they must be read and assigned to a variable; they cannot be read and assigned to a signal. As this is an algorithmic level model defined in a single entity it contains no input or outputs, nor does it contain any internal signals or associated timing. All computations use variables; variables are read from the test data file, the algorithm computes the result and variables are written to a results file.

VHDL algorithmic level model

library STD;

use STD.TEXTIO.all;

entity GCD_ALG is

end entity GCD_ALG;

architecture ALGORITHM of GCD_ALG is

--------------------------------------------

-- Declare test data file and results file

--------------------------------------------

file TestDataFile: text open

    read_mode is "gcd_ test_data.txt";

file ResultsFile: text open write_mode is

    "gcd_alg _test_results.txt";

begin

   GCD: process

      variable A_in, B_in, A, B, Swap, Y, Y_Ref: integer range 0 to 65535;

      variable TestData: line;

      variable BufLine: line;

      variable Passed: bit := '1';

   begin

      while not endfile(TestDataFile) loop

      -------------------------------------

      -- Read test data from file

      -------------------------------------

      readline(TestDataFile, TestData);

      read(TestData, A_in);

      read(TestData, B_in);

      read(TestData, Y_Ref);

      ------------------------------------

      -- Model GCD algorithm

      ------------------------------------

      A := A_in;

      B := B_in;

      if (A /= 0 and B /= 0) then

         while (B /= 0) loop

            while (A >= B) loop

                A := A - B;

            end loop;

            Swap:= A;

            A := B;

           B := Swap;

         end loop;

      else

         A := 0;

      end if;

      Y := A;

      ---------------------------------

      -- Test GCD algorithm

      ---------------------------------

      if (Y /= Y_Ref) then -- has failed

         Passed := '0';

         write(Bufline, st ring'("GCD Error: A="));

         write(Bufline, A_in);

         write(Bufline, string'(" B="));

         write(Bufline, B_in);

         write(Bufline, string'(" Y="));

         write(Bufline, Y);

         write(Bufline, string'(" Y_Ref="));

         write(Bufline, Y_Ref);

         writeline(ResultsFile, Bufline);

      end if;

    end loop;

  if (Passed = '1') then -- has passed

     write(Bufline, string' ("GCD algorithm test has passed"));

     writeline(ResultsFile, Bufline);

  end if;

 end process;

end architecture ALGORITHM;

Verilog algorithmic level model

The Verilog model also follows the same principle as defined above for the C model. A major difference in this model is that Verilog cannot read decimal integer values from a system file. Data read from a system file must be:1) read using one of the two language define system tasks, $readmemh or $readmemb and
2) stored in a memory, which has specific width and depth. This limits any read data to being in either hexadecimal or binary format. In this case a separate test d ata file is used "gcd_test_data_hex.txt" which has the test data specified in hexadecimal format.

Verilog algorithmic level model

module GCD_ALG;

parameter Width = 8;

reg [Width-1:0] A_in, B_in, A, B, Y, Y_Ref;

reg [Width-1:0] A_reg,B_reg,Swap;

parameter GCD_tests = 6;

integer N, M;

reg Passed, FailTime;

integer SimResults;

// Declare memory array for test data

// ----------------------------------

reg [Width-1:1] AB_Y_Ref_Arr[1:GCD_tests*3];

//----------------------------------

// Model GCD algorithm

//----------------------------------

always @(A or B)

   begin: GCD

     A = A_in;

     B = B_in;

     if (A != 0 && B != 0)

       while (B != 0)

         while (A >= B) begin

            A = A - B;

            Swap = A;

            A = B;

            B = Swap;

         end

     else

       A = 0;

       Y = A;

   end

//------------------------------

// Test GCD algorithm

//-----------------------------

initial begin

// Load contents of

// "gcd_test_data.txt" into array.

$readmemh("gcd_test_data_hex.txt", AB_Y_Ref_Arr);

// Open simulation results file

SimResults = $fopen("gcd.simres");

Passed = 1;

/ Set to 0 if fails

for (N=1; N<=GCD_tests; N=N+1) begin

   A_in = AB_Y_Ref_Arr[(N*3)+1];

   B_in = AB_Y_Ref_Arr[(N*3)+2];

   Y_Ref=AB_Y_Ref_Arr[(N*3)+3];

   #TestPeriod

   if (Y != Y_Ref) begin      // has failed

       Passed = 0;

       $fdisplay (SimResults, " GCD Error:

          A=%d B=%d Y=%d. Y should be %d", A_in, B_in, Y, Y_Ref);

   end

end

if (Passed == 1) // has passed

    $fdisplay (SimResults, "GCD algorithm test ha s passed");

    $fclose (SimResults);

    $finish;

end

endmodule

4.2.2 Designing RTL hardware models in VHDL and Verilog

The models have additional inputs and outputs over and above that of the algorithmic models. They are inputs Clock, Reset_N and Load, and the output Done. When Load is at logic 1 it signifies input data is available on inputs A and B, and are loaded into separate registers whose output signals are called A_hold and B_ hold. The extra output signal, Done, switches to a logic 1 to signify the greate st common divisor has been computed. It takes a number of clock cycles to comput e the GCD and is dependent upon the values of A and B.The models are broken down into three process (VHDL)/always (Verilog) statements.
First process/always statement LOAD_SWAP. Infers two registers which operate as follows:
1) When Reset_N is at a logic 0, A_hold and B_hold are set to zero.
2) When not 1) and Load is at logic 1, data on A and B is loaded into A_hold and B_hold.
3) When not 1) or 2) and A_hold is less than B_hold, values on A_hold and B_hold are swapped, that is, A_hold and B_hold are loaded into B_hold and A_hold respectively.
4) When not 1), 2) or 3), A_hold is reloaded, that is, it keeps the same value. The value of A_hold - B_hold, from the second process/always statement, is loaded into B_hold.
Second process/always statement SUBTRACT_TEST. The first if statement tests to see if A_hold is greater than or equal to B_hold. If it is, the subtraction, A_hold - B_hold, occurs and the result assigned to A_New ready to be loaded into B_hold on the next rising edge of the clock signal. If A_hold is less than B_hold, then subtraction cannot occur and A_New is assigned the value B_hold so that a swap occurs after the next rising edge of the clock signal. The second if statement checks to see if the value of B_hold has reached zero. If it has, signal Done is set to logic 1 and the value of A_ hold is passed to the output Y through an inferred multiplexer function.
It is a requirement of the problem to synthesize the generic model with 8-bit bus signals. This is easily achieved in Verilog model by setting the default parameter value Width to 8. This means it does not need to be separately instantiat ed before it can be synthesized and have the correct bit width. This is not the case in VHDL, which uses a generic. The value of the generic is only specified when the model is instantiated. Although the VHDL model will be instantiated in the test harness, the test harness is not synthesized. Therefore, in order to synthesize an 8-bit GCD circuit a separate synthesizable model must be used to instantiate the RTL level model which specifies the generic, Width, to be 8. The simulation test harness does not need to use this extra model as it too, will specify the generic, Width, to be 8.

VHDL RTL model

library IEEE;

use IEEE.STD_Logic_1164.all, IEEE.Numeric_STD.all;

entity GCD is

generic (Width: natural);

port (Clock,Reset,Load: in std_logic;

   A,B:   in unsigned(Width-1 downto 0);

   Done:  out std_logic;

   Y:     out unsigned(Width-1 downto 0));

end entity GCD;

architecture RTL of GCD is

   signal A_New,A_Hold,B_Hold: unsigned(Width-1 downto 0);

   signal A_lessthan_B: std_logic;

begin

----------------------------------------------------

-- Load 2 input registers and ensure B_Hold < A_Hold

---------------------------------------------------

LOAD_SWAP: process (Clock)

begin

   if rising_edge(Clock) then

     if (Reset = '0') then

       A_Hold <= (others => '0');

       B_Hold <= (others => '0');

     elsif (Load = '1') then

       A_Hold <= A;

       B_Hold <= B;

     else if (A_lessthan_B = '1') then

       A_Hold <= B_Hold;

       B_Hold <= A_New;

     else A_Hold <= A _New;

     end if;

   end if;

end process LOAD_SWAP;

SUBTRACT_TEST: process (A_Hold, B_Hold)

begin

   -------------------------------------------------------

   -- Subtract B_Hold from A_Hold if A_Hold >= B_Hold

   ------------------------------------------------------

   if (A_Hold >= B_Hold) then

      A_lessthan_B <= '0';

      A_New <= A_Hold - B_Hold;

   else

      A_lessthan_B <= '1';

      A_New <= A_Hold;

   end if;

   -------------------------------------------------

   -- Greatest common divisor found if B_Hold = 0

   -------------------------------------------------

   if (B_Hold = (others => '0')) then

      Done <= '1';

      Y <= A_Hold;

   else

      Done <= '0';

      Y <= (others => '0');

   end if;

end process SUBTRACT_TEST;

end architecture RTL;

Verilog RTL model

module GCD (Clock, Reset, Load, A, B, Done, Y);

parameter Width = 8;

input Clock, Reset, Load;

input [Width-1:0] A, B;

output Done;

output [Width-1:0] Y;

reg A_lessthan_B, Done;

reg [Width-1:0] A_New, A_Hold, B_Hold, Y;

//-----------------------------------------------------

// Load 2 input registers and ensure B_Hold < A_Hold

//-----------------------------------------------------

always @(posedge Clock)

    begin: LOAD_SWAP

       if (Reset) begin

           A_Hold = 0;

           B_Hold = 0;

       end

       else if (Load) begin

           A_Hold = A;

           B_Hold = B;

       end

       else if (A_lessthan_B) begin

           A_Hold = B_Hold;

           B_Hold = A_New;

       end

       else

           A_Hold = A_New;

    end

always @(A_Hold or B_Hold)

   begin: SUBTRACT_TEST

      //--------------------------------------------------

      // Subtract B_Hold from A_Hold if A_Hold >= B_Hold

      //--------------------------------------------------

      if (A_Hold >= B_Hold) begin

         A_lessthan_ B = 0;

         A_New = A_Hold - B_Hold;

      end

      else begin

         A_lessthan_B = 1;

         A_New = A_Hold;

      end

      //----------------------------------------------

      // Greatest common divisor found if B_Hold = 0

      //----------------------------------------------

      if (B_Hold == 0) begin

         Done = 1;

         Y = A_Hold;

      end

      else begin

         Done = 0;

         Y = 0;

      end

end

endmodule

5. Conclusions

The reasons for the importance of being able to model hardware in both VHDL and Verilog has been discussed. VHDL and Verilog has been extensively compared and contrasted in a neutral manner . A tutorial has been posed as a problem and solution to demonstrate some language differences and indicated that hardware modeled in one language can also be modeled in the other. Room did not allow test harness models to be included in this tutorial paper, but is shown in the book "HDL Chip Design" [1]. The choice of HDL is shown not to be based on technical capability, but on: personal preferences, EDA tool availability and commercial, business and marketing issues.REFERENCES: [1] HDL Chip Design, A Practical Guide for Designing, Synthesizing and Simulating ASICs and FPGAs using VHDL or Verilog by Douglas J Smith, published by Doone Publications.

Latest List of VLSI Projects for Electronics Engineering Students

VLSI – Very Large Scale integration technology involves designing integrated circuits (ICs) by combining thousands of transistors logically into a single chip by different logic circuits. These ICs eventually reduce the occupied circuit space when compared to the circuits with conventional ICs. Computational power and space utilizations are the main challenges of the VLSI design.

Implementing VLSI projects opens up a challenging and bright career for students as well as researchers. Some of the new trending areas of VLSI are Field Programmable Gate Array applications (FPGA), ASIC designs and SOCs. A list of some of the VLSI projects is given below for those students who are earnestly seeking projects in this field.

1. FPGA-Based Fault Emulation of Synchronous Sequential Circuits
2. Pragmatic Integration of SRAM Row Cache in Heterogeneous 3-D DRAM Architecture Using TSV
3. Built-in Self-Test Technique for Diagnosis of Delay Faults in Cluster-Based Field Programmable Gate Arrays
4. ASIC Design of Complex Multiplier
5. A Low Cost VLSI Implementation for Efficient Removal of Impulse Noise
6. FPGA Based Space Vector PWM Control IC For Three Phase Induction Motor Drive
7. VLSI Implementation of Auto Correlator and CORDIC Algorithm for OFDM Based WLAN
8. Automatic Road Extraction Using High Resolution Satellite Images
9. VHDL Design for Image Segmentation Using Gabor Filter for Disease Detection
10. A Low Complexity Turbo Decoder Architecture for Energy Efficient Wireless Sensor Networks
11. Improvement of The Orthogonal Code Convolution Capabilities Using FPGA Implementation
12. Design and Implementation of Floating Point ALU
13. CORDIC Design for Fixed Angle of Rotation
14. Product Reed-Solomon Codes for Implementing NAND Flash Controller on FPGA Chip
15. Statistical SRAM Read Access Yield Improvement Using Negative Capacitance Circuits
16. Power Management of MIMO Network Interfaces on Mobile Systems
17. Design of Data Encryption Standard for Data Encryption
18. Low Power and Area Efficient Carry Select Adder
19. Synthesis and Implementation of UART Using VHDL Codes
20. Improved Architectures for a Fused Floating-Point Add-Subtract Unit
21. An FPGA Based 1-Bit All Digital Transmitter Employing Delta-Sigma Modulation with RF Output for SDR
22. Optimizing Chain Search Usage in The BCH Decoder for High Error Rate Transmission
23. Digital Design of DS-CDMA Transmitter Using Verilog HDL and FPGA
24. Design and Implementation of Efficient Systolic Array Architecture
25. A VLSI-Based Robot Dynamics Learning Algorithm
26. A Versatile Multimedia Functional Unit Design Using the Spurious Power Suppression Technique
27. Design of Bus Bridge between AHB and OCP
28. Behavioral Synthesis of Asynchronous Circuits
29. Speed Optimization of a FPGA Based Modified Viterbi Decoder
30. Implementation of I2C Interface
31. A High-Speed/Low-Power Multiplier Using an Advanced Spurious Power Suppression Technique
32. Clamping Virtual Supply Voltage of Power Gated Circuits for Active Leakage Reduction and Gate Oxide Reliability
33. FPGA Based Power Efficient Channelizer for Software Defined Radio
34. VLSI Architecture and FPGA Prototyping of a Digital Camera for Image Security and Authentication
35. Operation Improvement of Indoor Robot
36. Design and Implementation of an ON-Chip Permutation Network for Multiprocessor System On-Chip
37. A Symbol-Rate Timing Synchronization Method for Low Power Wireless OFDM Systems
38. DMA Controller (Direct Memory Access ) Using VHDL/VLSI
39. Reconfigurable FFT Using CORDIC Based Architecture for MIMI-OFDM Receivers
40. Spurious Power Suppression Technique for Multimedia/DSP Applications
41. Efficiency of BCH Codes in Digital Image Watermarking
42. Dual Data Rate SD RAM Controller
43. Implementing Gabor Filter for Fingerprint Recognition Using Verilog HDL
44. Design of a Practical Nanometer Scale Redundant via Aware Standard Cell Library for Improved Redundant via 1 Insertion Rate
45. A Lossless Data Compression and Decompression Algorithm and Its Hardware Architecture
46. A Framework for Correction of Multi-Bit Soft Errors
47. Viterbi-Based Efficient Test Data Compression
48. Implementation of FFT/IFFT Blocks for OFDM
49. Wavelet Based Image Compression by VLSI Progressive Coding
50. VLSI Implementation of Fully Pipelined Multiplier Less 2d DCT/IDCT Architecture for Jpeg

After spending your valuable time while going through this list, we believe that you have got a fairly good idea of selecting the project topic of your choice from the VLSI projects’ list, and hope that you have enough confidence to take up any topic from the list. For further details and help about these projects you can write to us in the comments section given below.

source: https://www.elprocus.com/ieee-based-list-of-best-vlsi-projects-for-engineering-students-in-2014/